3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
12 #include <asm/ppc4xx-gpio.h>
16 #include <gdsys_fpga.h>
18 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
19 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
20 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
31 struct ihs_fpga
*fpga_ptr
[] = CONFIG_SYS_FPGA_PTR
;
43 char *s
= getenv("serial#");
45 puts("Board: CATCenter Neo");
57 static void print_fpga_info(void)
62 int fpga_state
= get_fpga_state(0);
64 unsigned hardware_version
;
65 unsigned feature_channels
;
68 if (fpga_state
& FPGA_STATE_DONE_FAILED
) {
69 printf(" done timed out\n");
73 if (fpga_state
& FPGA_STATE_REFLECTION_FAILED
) {
74 printf(" refelectione test failed\n");
78 FPGA_GET_REG(0, versions
, &versions
);
79 FPGA_GET_REG(0, fpga_version
, &fpga_version
);
80 FPGA_GET_REG(0, fpga_features
, &fpga_features
);
82 unit_type
= (versions
& 0xf000) >> 12;
83 hardware_version
= versions
& 0x000f;
84 feature_channels
= fpga_features
& 0x007f;
92 printf("UnitType %d(not supported)", unit_type
);
96 switch (hardware_version
) {
98 printf(" HW-Ver 3.00-3.12\n");
102 printf(" HW-Ver %d(not supported)\n",
107 printf(" FPGA V %d.%02d, features:",
108 fpga_version
/ 100, fpga_version
% 100);
110 printf(" %d channel(s)\n", feature_channels
);
113 int last_stage_init(void)
120 void gd405ep_init(void)
124 void gd405ep_set_fpga_reset(unsigned state
)
127 out_le16((void *)LATCH0_BASE
, CONFIG_SYS_LATCH0_RESET
);
128 out_le16((void *)LATCH1_BASE
, CONFIG_SYS_LATCH1_RESET
);
130 out_le16((void *)LATCH0_BASE
, CONFIG_SYS_LATCH0_BOOT
);
131 out_le16((void *)LATCH1_BASE
, CONFIG_SYS_LATCH1_BOOT
);
135 void gd405ep_setup_hw(void)
138 * set "startup-finished"-gpios
140 gpio_write_bit(21, 0);
141 gpio_write_bit(22, 1);
144 int gd405ep_get_fpga_done(unsigned fpga
)
147 * Neo hardware has no FPGA-DONE GPIO