board/gdsys/a38x/controlcenterdc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
   4  * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <miiphy.h>
  10 #include <tpm-v1.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm-generic/gpio.h>
  14
  15 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  16 #include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
  17
  18 #include "keyprogram.h"
  19 #include "dt_helpers.h"
  20 #include "hydra.h"
  21 #include "ihs_phys.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define ETH_PHY_CTRL_REG                0
  26 #define ETH_PHY_CTRL_POWER_DOWN_BIT     11
  27 #define ETH_PHY_CTRL_POWER_DOWN_MASK    (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
  28
  29 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW   0x7fffffff
  30 #define DB_GP_88F68XX_GPP_OUT_ENA_MID   0xffffefff
  31
  32 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW   0x0
  33 #define DB_GP_88F68XX_GPP_OUT_VAL_MID   0x00001000
  34 #define DB_GP_88F68XX_GPP_POL_LOW       0x0
  35 #define DB_GP_88F68XX_GPP_POL_MID       0x0
  36
  37 static int get_tpm(struct udevice **devp)
  38 {
  39         int rc;
  40
  41         rc = uclass_first_device_err(UCLASS_TPM, devp);
  42         if (rc) {
  43                 printf("Could not find TPM (ret=%d)\n", rc);
  44                 return CMD_RET_FAILURE;
  45         }
  46
  47         return 0;
  48 }
  49
  50 /*
  51  * Define the DDR layout / topology here in the board file. This will
  52  * be used by the DDR3 init code in the SPL U-Boot version to configure
  53  * the DDR3 controller.
  54  */
  55 static struct mv_ddr_topology_map ddr_topology_map = {
  56         DEBUG_LEVEL_ERROR,
  57         0x1, /* active interfaces */
  58         /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  59         { { { {0x1, 0, 0, 0},
  60               {0x1, 0, 0, 0},
  61               {0x1, 0, 0, 0},
  62               {0x1, 0, 0, 0},
  63               {0x1, 0, 0, 0} },
  64             SPEED_BIN_DDR_1600K,        /* speed_bin */
  65             MV_DDR_DEV_WIDTH_16BIT,     /* memory_width */
  66             MV_DDR_DIE_CAP_4GBIT,       /* mem_size */
  67             DDR_FREQ_533,               /* frequency */
  68             0, 0,                       /* cas_wl cas_l */
  69             MV_DDR_TEMP_LOW,            /* temperature */
  70             MV_DDR_TIM_DEFAULT} },      /* timing */
  71         BUS_MASK_32BIT,                 /* Busses mask */
  72         MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
  73         { {0} },                        /* raw spd data */
  74         {0}                             /* timing parameters */
  75
  76 };
  77
  78 static struct serdes_map serdes_topology_map[] = {
  79         {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  80         {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  81         /* SATA tx polarity is inverted */
  82         {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
  83         {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  84         {DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  85         {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
  86 };
  87
  88 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  89 {
  90         *serdes_map_array = serdes_topology_map;
  91         *count = ARRAY_SIZE(serdes_topology_map);
  92         return 0;
  93 }
  94
  95 void board_pex_config(void)
  96 {
  97 #ifdef CONFIG_SPL_BUILD
  98         uint k;
  99         struct gpio_desc gpio = {};
 100
 101         if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
 102                 /* prepare FPGA reconfiguration */
 103                 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
 104                 dm_gpio_set_value(&gpio, 0);
 105
 106                 /* give lunatic PCIe clock some time to stabilize */
 107                 mdelay(500);
 108
 109                 /* start FPGA reconfiguration */
 110                 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
 111         }
 112
 113         /* wait for FPGA done */
 114         if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
 115                 for (k = 0; k < 20; ++k) {
 116                         if (dm_gpio_get_value(&gpio)) {
 117                                 printf("FPGA done after %u rounds\n", k);
 118                                 break;
 119                         }
 120                         mdelay(100);
 121                 }
 122         }
 123
 124         /* disable FPGA reset */
 125         if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
 126                 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
 127                 dm_gpio_set_value(&gpio, 1);
 128         }
 129
 130         /* wait for FPGA ready */
 131         if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
 132                 for (k = 0; k < 2; ++k) {
 133                         if (!dm_gpio_get_value(&gpio))
 134                                 break;
 135                         mdelay(100);
 136                 }
 137         }
 138 #endif
 139 }
 140
 141 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
 142 {
 143         return &ddr_topology_map;
 144 }
 145
 146 int board_early_init_f(void)
 147 {
 148 #ifdef CONFIG_SPL_BUILD
 149         /* Configure MPP */
 150         writel(0x00111111, MVEBU_MPP_BASE + 0x00);
 151         writel(0x40040000, MVEBU_MPP_BASE + 0x04);
 152         writel(0x00466444, MVEBU_MPP_BASE + 0x08);
 153         writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
 154         writel(0x44400000, MVEBU_MPP_BASE + 0x10);
 155         writel(0x20000334, MVEBU_MPP_BASE + 0x14);
 156         writel(0x40000000, MVEBU_MPP_BASE + 0x18);
 157         writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
 158
 159         /* Set GPP Out value */
 160         writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
 161         writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
 162
 163         /* Set GPP Polarity */
 164         writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
 165         writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
 166
 167         /* Set GPP Out Enable */
 168         writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
 169         writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
 170 #endif
 171
 172         return 0;
 173 }
 174
 175 int board_init(void)
 176 {
 177         /* Address of boot parameters */
 178         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 179
 180         return 0;
 181 }
 182
 183 #ifndef CONFIG_SPL_BUILD
 184 void init_host_phys(struct mii_dev *bus)
 185 {
 186         uint k;
 187
 188         for (k = 0; k < 2; ++k) {
 189                 struct phy_device *phydev;
 190
 191                 phydev = phy_find_by_mask(bus, 1 << k,
 192                                           PHY_INTERFACE_MODE_SGMII);
 193
 194                 if (phydev)
 195                         phy_config(phydev);
 196         }
 197 }
 198
 199 int ccdc_eth_init(void)
 200 {
 201         uint k;
 202         uint octo_phy_mask = 0;
 203         int ret;
 204         struct mii_dev *bus;
 205
 206         /* Init SoC's phys */
 207         bus = miiphy_get_dev_by_name("ethernet@34000");
 208
 209         if (bus)
 210                 init_host_phys(bus);
 211
 212         bus = miiphy_get_dev_by_name("ethernet@70000");
 213
 214         if (bus)
 215                 init_host_phys(bus);
 216
 217         /* Init octo phys */
 218         octo_phy_mask = calculate_octo_phy_mask();
 219
 220         printf("IHS PHYS: %08x", octo_phy_mask);
 221
 222         ret = init_octo_phys(octo_phy_mask);
 223
 224         if (ret)
 225                 return ret;
 226
 227         printf("\n");
 228
 229         if (!get_fpga()) {
 230                 puts("fpga was NULL\n");
 231                 return 1;
 232         }
 233
 234         /* reset all FPGA-QSGMII instances */
 235         for (k = 0; k < 80; ++k)
 236                 writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
 237
 238         udelay(100);
 239
 240         for (k = 0; k < 80; ++k)
 241                 writel(0, get_fpga()->qsgmii_port_state[k]);
 242         return 0;
 243 }
 244
 245 #endif
 246
 247 int board_late_init(void)
 248 {
 249 #ifndef CONFIG_SPL_BUILD
 250         hydra_initialize();
 251 #endif
 252         return 0;
 253 }
 254
 255 int board_fix_fdt(void *rw_fdt_blob)
 256 {
 257         struct udevice *bus = NULL;
 258         uint k;
 259         char name[64];
 260         int err;
 261
 262         err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
 263
 264         if (err) {
 265                 printf("Could not get I2C bus.\n");
 266                 return err;
 267         }
 268
 269         for (k = 0x21; k <= 0x26; k++) {
 270                 snprintf(name, 64,
 271                          "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
 272
 273                 if (!dm_i2c_simple_probe(bus, k))
 274                         fdt_disable_by_ofname(rw_fdt_blob, name);
 275         }
 276
 277         return 0;
 278 }
 279
 280 int last_stage_init(void)
 281 {
 282         struct udevice *tpm;
 283         int ret;
 284
 285 #ifndef CONFIG_SPL_BUILD
 286         ccdc_eth_init();
 287 #endif
 288         ret = get_tpm(&tpm);
 289         if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) ||
 290             tpm_continue_self_test(tpm)) {
 291                 return 1;
 292         }
 293
 294         mdelay(37);
 295
 296         flush_keys(tpm);
 297         load_and_run_keyprog(tpm);
 298
 299         return 0;
 300 }