board/gdsys/gdppc440etx/gdppc440etx.c

   1 /*
   2  * (C) Copyright 2008
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * Based on board/amcc/yosemite/yosemite.c
   6  * (C) Copyright 2006-2007
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <ppc4xx.h>
  30 #include <asm/processor.h>
  31 #include <asm/io.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 /* info for FLASH chips */
  36 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  37
  38 int board_early_init_f(void)
  39 {
  40         register uint reg;
  41
  42         /*
  43          * Setup the external bus controller/chip selects
  44          */
  45         mfebc(EBC0_CFG, reg);
  46         mtebc(EBC0_CFG, reg | 0x04000000);              /* Set ATC */
  47
  48         /*
  49          * Setup the GPIO pins
  50          */
  51
  52         /* setup Address lines for flash size 64Meg. */
  53         out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
  54         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
  55         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
  56
  57         /* setup emac */
  58         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
  59         out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
  60         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
  61         out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
  62         out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
  63
  64         /* UART0 and UART1*/
  65         out32(GPIO1_TCR, in32(GPIO1_TCR)     | 0x16000000);
  66         out32(GPIO1_OSRL, in32(GPIO1_OSRL)   | 0x02180000);
  67         out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
  68         out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
  69
  70         /* disable boot-eeprom WP */
  71         out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
  72         out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
  73         out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
  74         out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
  75         out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
  76
  77         /* external interrupts IRQ0...3 */
  78         out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
  79         out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
  80         out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
  81
  82
  83         /*
  84          * Setup the interrupt controller polarities, triggers, etc.
  85          */
  86         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  87         mtdcr(UIC0ER, 0x00000000);      /* disable all */
  88         mtdcr(UIC0CR, 0x00000009);      /* ATI & UIC1 crit are critical */
  89         mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
  90         mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
  91         mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
  92         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  93
  94         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  95         mtdcr(UIC1ER, 0x00000000);      /* disable all */
  96         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  97         mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
  98         mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
  99         mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
 100         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 101
 102         /*
 103          * Setup other serial configuration
 104          */
 105         mfsdr(SDR0_PCI0, reg);
 106         mtsdr(SDR0_PCI0, 0x80000000 | reg);     /* PCI arbiter enabled */
 107         mtsdr(SDR0_PFC0, 0x00003e00);   /* Pin function */
 108         mtsdr(SDR0_PFC1, 0x00048000);   /* Pin function: UART0 has 4 pins */
 109
 110         return 0;
 111 }
 112
 113 int misc_init_r(void)
 114 {
 115         uint pbcr;
 116         int size_val;
 117         uint sz;
 118
 119         /* Re-do sizing to get full correct info */
 120         mfebc(PB0CR, pbcr);
 121
 122         if (gd->bd->bi_flashsize > 0x08000000)
 123                 panic("Max. flash banksize is 128 MB!\n");
 124
 125         for (sz = gd->bd->bi_flashsize, size_val = 7;
 126             ((sz & 0x08000000) == 0) && (size_val > 0); --size_val)
 127                 sz <<= 1;
 128
 129         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 130         mtebc(PB0CR, pbcr);
 131
 132         /* adjust flash start and offset */
 133         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 134         gd->bd->bi_flashoffset = 0;
 135
 136         /* Monitor protection ON by default */
 137         (void)flash_protect(FLAG_PROTECT_SET,
 138                             -CONFIG_SYS_MONITOR_LEN,
 139                             0xffffffff,
 140                             &flash_info[0]);
 141
 142         return 0;
 143 }
 144
 145 int checkboard(void)
 146 {
 147         char *s = getenv("serial#");
 148
 149         printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module");
 150
 151         if (s != NULL) {
 152                 puts(", serial# ");
 153                 puts(s);
 154         }
 155         putc('\n');
 156
 157         return 0;
 158 }
 159
 160 /*
 161  * pci_pre_init
 162  *
 163  * This routine is called just prior to registering the hose and gives
 164  * the board the opportunity to check things. Returning a value of zero
 165  * indicates that things are bad & PCI initialization should be aborted.
 166  *
 167  *      Different boards may wish to customize the pci controller structure
 168  *      (add regions, override default access routines, etc) or perform
 169  *      certain pre-initialization actions.
 170  *
 171  */
 172 #if defined(CONFIG_PCI)
 173 int pci_pre_init(struct pci_controller *hose)
 174 {
 175         unsigned long addr;
 176
 177         /*
 178          * Set priority for all PLB3 devices to 0.
 179          * Set PLB3 arbiter to fair mode.
 180          */
 181         mfsdr(SD0_AMP1, addr);
 182         mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
 183         addr = mfdcr(PLB3_ACR);
 184         mtdcr(PLB3_ACR, addr | 0x80000000);
 185
 186         /*
 187          * Set priority for all PLB4 devices to 0.
 188          */
 189         mfsdr(SD0_AMP0, addr);
 190         mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
 191         addr = mfdcr(PLB4_ACR) | 0xa0000000;    /* Was 0x8---- */
 192         mtdcr(PLB4_ACR, addr);
 193
 194         /*
 195          * Set Nebula PLB4 arbiter to fair mode.
 196          */
 197         /* Segment0 */
 198         addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
 199         addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
 200         addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
 201         addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
 202         mtdcr(PLB0_ACR, addr);
 203
 204         /* Segment1 */
 205         addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
 206         addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
 207         addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
 208         addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
 209         mtdcr(PLB1_ACR, addr);
 210
 211         /* enable 66 MHz ext. Clock */
 212         out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
 213         out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000);
 214
 215         return 1;
 216 }
 217 #endif  /* defined(CONFIG_PCI) */
 218
 219 /*
 220  * pci_target_init
 221  *
 222  * The bootstrap configuration provides default settings for the pci
 223  * inbound map (PIM). But the bootstrap config choices are limited and
 224  * may not be sufficient for a given board.
 225  *
 226  */
 227 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 228 void pci_target_init(struct pci_controller *hose)
 229 {
 230         /*
 231          * Set up Direct MMIO registers
 232          */
 233
 234         /*
 235          * PowerPC440 EP PCI Master configuration.
 236          * Map one 1Gig range of PLB/processor addresses to PCI memory space.
 237          *       PLB address 0xA0000000-0xDFFFFFFF
 238          *   ==> PCI address 0xA0000000-0xDFFFFFFF
 239          *   Use byte reversed out routines to handle endianess.
 240          * Make this region non-prefetchable.
 241          */
 242         out32r(PCIX0_PMM0MA, 0x00000000);       /* disabled b4 setting */
 243         out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
 244         out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
 245         out32r(PCIX0_PMM0PCIHA, 0x00000000);
 246         out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
 247
 248         out32r(PCIX0_PMM1MA, 0x00000000);       /* disabled b4 setting */
 249         out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
 250         out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
 251         out32r(PCIX0_PMM1PCIHA, 0x00000000);
 252         out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
 253
 254         out32r(PCIX0_PTM1MS, 0x00000001);
 255         out32r(PCIX0_PTM1LA, 0);
 256         out32r(PCIX0_PTM2MS, 0);
 257         out32r(PCIX0_PTM2LA, 0);
 258
 259         /*
 260          * Set up Configuration registers
 261          */
 262
 263         /* Program the board's subsystem id/vendor id */
 264         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 265                               CONFIG_SYS_PCI_SUBSYS_VENDORID);
 266         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 267
 268         /* Configure command register as bus master */
 269         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 270
 271         /* 240nS PCI clock */
 272         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 273
 274         /* No error reporting */
 275         pci_write_config_word(0, PCI_ERREN, 0);
 276
 277         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 278
 279 }
 280 #endif  /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 281
 282 /*
 283  *  pci_master_init
 284  *
 285  */
 286 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 287 void pci_master_init(struct pci_controller *hose)
 288 {
 289         unsigned short temp_short;
 290
 291         /*
 292          * Write the PowerPC440 EP PCI Configuration regs.
 293          *   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 294          *   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 295          */
 296         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 297         pci_write_config_word(0, PCI_COMMAND,
 298                               temp_short | PCI_COMMAND_MASTER |
 299                               PCI_COMMAND_MEMORY);
 300 }
 301 #endif  /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 302
 303 /*
 304  *  is_pci_host
 305  *
 306  *      This routine is called to determine if a pci scan should be
 307  *      performed. With various hardware environments (especially cPCI and
 308  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 309  *      bit in the strap register, or generic host/adapter assumptions.
 310  *
 311  *      Rather than hard-code a bad assumption in the general 440 code, the
 312  *      440 pci code requires the board to decide at runtime.
 313  *
 314  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 315  *
 316  *
 317  */
 318 #if defined(CONFIG_PCI)
 319 int is_pci_host(struct pci_controller *hose)
 320 {
 321         return 1;
 322 }
 323 #endif  /* defined(CONFIG_PCI) */