board/gdsys/intip/intip.c

   1 /*
   2  * (C) Copyright 2009
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * Based on board/amcc/canyonlands/canyonlands.c
   6  * (C) Copyright 2008
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/ppc440.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <i2c.h>
  30 #include <asm/processor.h>
  31 #include <asm/io.h>
  32 #include <asm/mmu.h>
  33 #include <asm/4xx_pcie.h>
  34 #include <asm/ppc4xx-gpio.h>
  35
  36 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #define CONFIG_SYS_BCSR3_PCIE           0x10
  41
  42 int board_early_init_f(void)
  43 {
  44         /*
  45          * Setup the interrupt controller polarities, triggers, etc.
  46          */
  47         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  48         mtdcr(UIC0ER, 0x00000000);      /* disable all */
  49         mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
  50         mtdcr(UIC0PR, 0xffffffff);      /* per ref-board manual */
  51         mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
  52         mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
  53         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  54
  55         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  56         mtdcr(UIC1ER, 0x00000000);      /* disable all */
  57         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  58         mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
  59         mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
  60         mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
  61         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  62
  63         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  64         mtdcr(UIC2ER, 0x00000000);      /* disable all */
  65         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
  66         mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
  67         mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
  68         mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
  69         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  70
  71         mtdcr(UIC3SR, 0xffffffff);      /* clear all */
  72         mtdcr(UIC3ER, 0x00000000);      /* disable all */
  73         mtdcr(UIC3CR, 0x00000000);      /* all non-critical */
  74         mtdcr(UIC3PR, 0xffffffff);      /* per ref-board manual */
  75         mtdcr(UIC3TR, 0x00000000);      /* per ref-board manual */
  76         mtdcr(UIC3VR, 0x00000000);      /* int31 highest, base=0x000 */
  77         mtdcr(UIC3SR, 0xffffffff);      /* clear all */
  78
  79         /*
  80          * Configure PFC (Pin Function Control) registers
  81          * enable GPIO 49-63
  82          * UART0: 4 pins
  83          */
  84         mtsdr(SDR0_PFC0, 0x00007fff);
  85         mtsdr(SDR0_PFC1, 0x00040000);
  86
  87         /* Enable PCI host functionality in SDR0_PCI0 */
  88         mtsdr(SDR0_PCI0, 0xe0000000);
  89
  90         mtsdr(SDR0_SRST1, 0);   /* Pull AHB out of reset default=1 */
  91
  92         /* Setup PLB4-AHB bridge based on the system address map */
  93         mtdcr(AHB_TOP, 0x8000004B);
  94         mtdcr(AHB_BOT, 0x8000004B);
  95
  96         /*
  97         * Configure USB-STP pins as alternate and not GPIO
  98         * It seems to be neccessary to configure the STP pins as GPIO
  99         * input at powerup (perhaps while USB reset is asserted). So
 100         * we configure those pins to their "real" function now.
 101         */
 102         gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 103         gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
 104
 105         /* Trigger board component reset */
 106         out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
 107         out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
 108         udelay(50);
 109         out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf);
 110         out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf);
 111         udelay(50);
 112         out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
 113         out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
 114
 115         return 0;
 116 }
 117
 118 int get_cpu_num(void)
 119 {
 120         int cpu = NA_OR_UNKNOWN_CPU;
 121
 122         return cpu;
 123 }
 124
 125 int checkboard(void)
 126 {
 127         char buf[64];
 128         int i = getenv_f("serial#", buf, sizeof(buf));
 129
 130 #ifdef CONFIG_DEVCONCENTER
 131         printf("Board: DevCon-Center");
 132 #else
 133         printf("Board: Intip");
 134 #endif
 135
 136         if (i > 0) {
 137                 puts(", serial# ");
 138                 puts(buf);
 139         }
 140         putc('\n');
 141
 142         return 0;
 143 }
 144
 145 int board_early_init_r(void)
 146 {
 147         /*
 148          * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH
 149          * (Spansion 29GL512), but the boot EBC mapping only supports a maximum
 150          * of 16MBytes (4.ff00.0000 - 4.ffff.ffff).
 151          * To solve this problem, the FLASH has to get remapped to another
 152          * EBC address which accepts bigger regions:
 153          *
 154          * 0xfn00.0000 -> 4.cn00.0000
 155          */
 156
 157         u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ?
 158                 EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
 159
 160         /* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
 161         mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L
 162                 | bxcr_bw
 163                 | EBC_BXCR_BU_RW
 164                 | EBC_BXCR_BW_16BIT);
 165
 166         /* Remove TLB entry of boot EBC mapping */
 167         remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
 168
 169         /* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
 170         program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
 171                         CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
 172
 173         /*
 174          * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
 175          * 0xfc00.0000 is possible
 176          */
 177
 178         /*
 179          * Clear potential errors resulting from auto-calibration.
 180          * If not done, then we could get an interrupt later on when
 181          * exceptions are enabled.
 182          */
 183         set_mcsr(get_mcsr());
 184
 185         return 0;
 186 }
 187
 188 int misc_init_r(void)
 189 {
 190         u32 sdr0_srst1 = 0;
 191         u32 eth_cfg;
 192
 193         /*
 194          * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
 195          * This is board specific, so let's do it here.
 196          */
 197         mfsdr(SDR0_ETH_CFG, eth_cfg);
 198         /* disable SGMII mode */
 199         eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
 200                      SDR0_ETH_CFG_SGMII1_ENABLE |
 201                      SDR0_ETH_CFG_SGMII0_ENABLE);
 202         /* Set the for 2 RGMII mode */
 203         /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
 204         eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
 205         eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
 206         mtsdr(SDR0_ETH_CFG, eth_cfg);
 207
 208         /*
 209          * The AHB Bridge core is held in reset after power-on or reset
 210          * so enable it now
 211          */
 212         mfsdr(SDR0_SRST1, sdr0_srst1);
 213         sdr0_srst1 &= ~SDR0_SRST1_AHB;
 214         mtsdr(SDR0_SRST1, sdr0_srst1);
 215
 216         return 0;
 217 }
 218
 219 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 220 extern void __ft_board_setup(void *blob, bd_t *bd);
 221
 222 void ft_board_setup(void *blob, bd_t *bd)
 223 {
 224         __ft_board_setup(blob, bd);
 225
 226         fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
 227                              "disabled", sizeof("disabled"), 1);
 228
 229         fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
 230                              "disabled", sizeof("disabled"), 1);
 231 }
 232 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */