board/gen860t/fpga.c

   1 /*
   2  * (C) Copyright 2002
   3  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
   4  * Keith Outwater, keith_outwater@mvis.com.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  *
  24  */
  25
  26 /*
  27  * Virtex2 FPGA configuration support for the GEN860T computer
  28  */
  29
  30 #include <common.h>
  31 #include <virtex2.h>
  32 #include <command.h>
  33 #include "fpga.h"
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #if defined(CONFIG_FPGA)
  38
  39 #if 0
  40 #define GEN860T_FPGA_DEBUG
  41 #endif
  42
  43 #ifdef GEN860T_FPGA_DEBUG
  44 #define PRINTF(fmt,args...)     printf (fmt ,##args)
  45 #else
  46 #define PRINTF(fmt,args...)
  47 #endif
  48
  49 /*
  50  * Port bit numbers for the Selectmap controls
  51  */
  52 #define FPGA_INIT_BIT_NUM               22      /* PB22 */
  53 #define FPGA_RESET_BIT_NUM              11      /* PC11 */
  54 #define FPGA_DONE_BIT_NUM               16      /* PB16 */
  55 #define FPGA_PROGRAM_BIT_NUM    7       /* PA7  */
  56
  57 /* Note that these are pointers to code that is in Flash.  They will be
  58  * relocated at runtime.
  59  */
  60 Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
  61         fpga_pre_config_fn,
  62         fpga_pgm_fn,
  63         fpga_init_fn,
  64         fpga_err_fn,
  65         fpga_done_fn,
  66         fpga_clk_fn,
  67         fpga_cs_fn,
  68         fpga_wr_fn,
  69         fpga_read_data_fn,
  70         fpga_write_data_fn,
  71         fpga_busy_fn,
  72         fpga_abort_fn,
  73         fpga_post_config_fn
  74 };
  75
  76 Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
  77         {Xilinx_Virtex2,
  78          slave_selectmap,
  79          XILINX_XC2V3000_SIZE,
  80          (void *) &fpga_fns,
  81          0}
  82 };
  83
  84 /*
  85  * Display FPGA revision information
  86  */
  87 void print_fpga_revision (void)
  88 {
  89         vu_long *rev_p = (vu_long *) 0x60000008;
  90
  91         printf ("FPGA Revision 0x%.8lx"
  92                 " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
  93                 *rev_p,
  94                 ((*rev_p >> 28) & 0xf),
  95                 ((*rev_p >> 20) & 0xff),
  96                 ((*rev_p >> 12) & 0xff),
  97                 ((*rev_p >> 8) & 0xf), (*rev_p & 0xff));
  98 }
  99
 100
 101 /*
 102  * Perform a simple test of the FPGA to processor interface using the FPGA's
 103  * inverting bus test register.  The great thing about doing a read/write
 104  * test on a register that inverts it's contents is that you avoid any
 105  * problems with bus charging.
 106  * Return 0 on failure, 1 on success.
 107  */
 108 int test_fpga_ibtr (void)
 109 {
 110         vu_long *ibtr_p = (vu_long *) 0x60000010;
 111         vu_long readback;
 112         vu_long compare;
 113         int i;
 114         int j;
 115         int k;
 116         int pass = 1;
 117
 118         static const ulong bitpattern[] = {
 119                 0xdeadbeef,     /* magic ID pattern for debug   */
 120                 0x00000001,     /* single bit                                   */
 121                 0x00000003,     /* two adjacent bits                    */
 122                 0x00000007,     /* three adjacent bits                  */
 123                 0x0000000F,     /* four adjacent bits                   */
 124                 0x00000005,     /* two non-adjacent bits                */
 125                 0x00000015,     /* three non-adjacent bits              */
 126                 0x00000055,     /* four non-adjacent bits               */
 127                 0xaaaaaaaa,     /* alternating 1/0                              */
 128         };
 129
 130         for (i = 0; i < 1024; i++) {
 131                 for (j = 0; j < 31; j++) {
 132                         for (k = 0;
 133                              k < sizeof (bitpattern) / sizeof (bitpattern[0]);
 134                              k++) {
 135                                 *ibtr_p = compare = (bitpattern[k] << j);
 136                                 readback = *ibtr_p;
 137                                 if (readback != ~compare) {
 138                                         printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback);
 139                                         pass = 0;
 140                                         break;
 141                                 }
 142                         }
 143                         if (!pass)
 144                                 break;
 145                 }
 146                 if (!pass)
 147                         break;
 148         }
 149         if (pass) {
 150                 printf ("FPGA inverting bus test passed\n");
 151                 print_fpga_revision ();
 152         } else {
 153                 printf ("** FPGA inverting bus test failed\n");
 154         }
 155         return pass;
 156 }
 157
 158
 159 /*
 160  * Set the active-low FPGA reset signal.
 161  */
 162 void fpga_reset (int assert)
 163 {
 164         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 165
 166         PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__);
 167         if (assert) {
 168                 immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM);
 169                 PRINTF ("asserted\n");
 170         } else {
 171                 immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM);
 172                 PRINTF ("deasserted\n");
 173         }
 174 }
 175
 176
 177 /*
 178  * Initialize the SelectMap interface.  We assume that the mode and the
 179  * initial state of all of the port pins have already been set!
 180  */
 181 void fpga_selectmap_init (void)
 182 {
 183         PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
 184                 __LINE__);
 185         fpga_pgm_fn (FALSE, FALSE, 0);  /* make sure program pin is inactive */
 186 }
 187
 188
 189 /*
 190  * Initialize the fpga.  Return 1 on success, 0 on failure.
 191  */
 192 int gen860t_init_fpga (void)
 193 {
 194         int i;
 195
 196         PRINTF ("%s:%d: Initialize FPGA interface\n",
 197                 __FUNCTION__, __LINE__);
 198         fpga_init ();
 199         fpga_selectmap_init ();
 200
 201         for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
 202                 PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
 203                 fpga_add (fpga_xilinx, &fpga[i]);
 204         }
 205         return 1;
 206 }
 207
 208
 209 /*
 210  * Set the FPGA's active-low SelectMap program line to the specified level
 211  */
 212 int fpga_pgm_fn (int assert, int flush, int cookie)
 213 {
 214         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 215
 216         PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
 217
 218         if (assert) {
 219                 immap->im_ioport.iop_padat &=
 220                         ~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
 221                 PRINTF ("asserted\n");
 222         } else {
 223                 immap->im_ioport.iop_padat |=
 224                         (0x8000 >> FPGA_PROGRAM_BIT_NUM);
 225                 PRINTF ("deasserted\n");
 226         }
 227         return assert;
 228 }
 229
 230
 231 /*
 232  * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
 233  * asserted (low).
 234  */
 235 int fpga_init_fn (int cookie)
 236 {
 237         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 238
 239         PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
 240         if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
 241                 PRINTF ("high\n");
 242                 return 0;
 243         } else {
 244                 PRINTF ("low\n");
 245                 return 1;
 246         }
 247 }
 248
 249
 250 /*
 251  * Test the state of the active-high FPGA DONE pin
 252  */
 253 int fpga_done_fn (int cookie)
 254 {
 255         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 256
 257         PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
 258         if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
 259                 PRINTF ("high\n");
 260                 return FPGA_SUCCESS;
 261         } else {
 262                 PRINTF ("low\n");
 263                 return FPGA_FAIL;
 264         }
 265 }
 266
 267
 268 /*
 269  * Read FPGA SelectMap data.
 270  */
 271 int fpga_read_data_fn (unsigned char *data, int cookie)
 272 {
 273         vu_char *p = (vu_char *) SELECTMAP_BASE;
 274
 275         *data = *p;
 276 #if 0
 277         PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data);
 278 #endif
 279         return (int) data;
 280 }
 281
 282
 283 /*
 284  * Write data to the FPGA SelectMap port
 285  */
 286 int fpga_write_data_fn (unsigned char data, int flush, int cookie)
 287 {
 288         vu_char *p = (vu_char *) SELECTMAP_BASE;
 289
 290 #if 0
 291         PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data);
 292 #endif
 293         *p = data;
 294         return (int) data;
 295 }
 296
 297
 298 /*
 299  * Abort and FPGA operation
 300  */
 301 int fpga_abort_fn (int cookie)
 302 {
 303         PRINTF ("%s:%d: FPGA program sequence aborted\n",
 304                 __FUNCTION__, __LINE__);
 305         return FPGA_FAIL;
 306 }
 307
 308
 309 /*
 310  * FPGA pre-configuration function. Just make sure that
 311  * FPGA reset is asserted to keep the FPGA from starting up after
 312  * configuration.
 313  */
 314 int fpga_pre_config_fn (int cookie)
 315 {
 316         PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
 317         fpga_reset (TRUE);
 318         return 0;
 319 }
 320
 321
 322 /*
 323  * FPGA post configuration function. Blip the FPGA reset line and then see if
 324  * the FPGA appears to be running.
 325  */
 326 int fpga_post_config_fn (int cookie)
 327 {
 328         int rc;
 329
 330         PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
 331         fpga_reset (TRUE);
 332         udelay (1000);
 333         fpga_reset (FALSE);
 334         udelay (1000);
 335
 336         /*
 337          * Use the FPGA,s inverting bus test register to do a simple test of the
 338          * processor interface.
 339          */
 340         rc = test_fpga_ibtr ();
 341         return rc;
 342 }
 343
 344
 345 /*
 346  * Clock, chip select and write signal assert functions and error check
 347  * and busy functions.  These are only stubs because the GEN860T selectmap
 348  * interface handles sequencing of control signals automatically (it uses
 349  * a memory-mapped interface to the FPGA SelectMap port).  The design of
 350  * the interface guarantees that the SelectMap port cannot be overrun so
 351  * no busy check is needed.  A configuration error is signalled by INIT
 352  * going low during configuration, so there is no need for a separate error
 353  * function.
 354  */
 355 int fpga_clk_fn (int assert_clk, int flush, int cookie)
 356 {
 357         return assert_clk;
 358 }
 359
 360 int fpga_cs_fn (int assert_cs, int flush, int cookie)
 361 {
 362         return assert_cs;
 363 }
 364
 365 int fpga_wr_fn (int assert_write, int flush, int cookie)
 366 {
 367         return assert_write;
 368 }
 369
 370 int fpga_err_fn (int cookie)
 371 {
 372         return 0;
 373 }
 374
 375 int fpga_busy_fn (int cookie)
 376 {
 377         return 0;
 378 }
 379 #endif