board/gth2/lowlevel_init.S

   1 /* Memory sub-system initialization code */
   2
   3 #include <config.h>
   4 #include <version.h>
   5 #include <asm/regdef.h>
   6 #include <asm/au1x00.h>
   7 #include <asm/mipsregs.h>
   8
   9 #define CP0_Config0             $16
  10 #define MEM_1MS                 ((CFG_MHZ) * 1000)
  11 #define GPIO_RJ1LY     (1<<22)
  12 #define GPIO_CFRESET   (1<<10)
  13
  14         .text
  15         .set noreorder
  16         .set mips32
  17
  18         .globl  lowlevel_init
  19 lowlevel_init:
  20         /*
  21          * Step 2) Establish Status Register
  22          * (set BEV, clear ERL, clear EXL, clear IE)
  23          */
  24         li      t1, 0x00400000
  25         mtc0    t1, CP0_STATUS
  26
  27         /*
  28          * Step 3) Establish CP0 Config0
  29          * (set OD, set K0=3)
  30          */
  31         li      t1, 0x00080003
  32         mtc0    t1, CP0_CONFIG
  33
  34         /*
  35          * Step 4) Disable Watchpoint facilities
  36          */
  37         li t1, 0x00000000
  38         mtc0    t1, CP0_WATCHLO
  39         mtc0    t1, CP0_IWATCHLO
  40         /*
  41          * Step 5) Disable the performance counters
  42          */
  43         mtc0    zero, CP0_PERFORMANCE
  44         nop
  45
  46         /*
  47          * Step 6) Establish EJTAG Debug register
  48          */
  49         mtc0    zero, CP0_DEBUG
  50         nop
  51
  52         /*
  53          * Step 7) Establish Cause
  54          * (set IV bit)
  55          */
  56         li      t1, 0x00800000
  57         mtc0    t1, CP0_CAUSE
  58
  59         /* Establish Wired (and Random) */
  60         mtc0    zero, CP0_WIRED
  61         nop
  62
  63         /* No workaround if running from ram */
  64         lui     t0, 0xffc0
  65         lui     t3, 0xbfc0
  66         and     t1, ra, t0
  67         bne     t1, t3, noCacheJump
  68         nop
  69
  70         /*** From AMD YAMON ***/
  71         /*
  72          * Step 8) Initialize the caches
  73          */
  74         li              t0, (16*1024)
  75         li              t1, 32
  76         li              t2, 0x80000000
  77         addu    t3, t0, t2
  78 cacheloop:
  79         cache   0, 0(t2)
  80         cache   1, 0(t2)
  81         addu    t2, t1
  82         bne             t2, t3, cacheloop
  83         nop
  84
  85         /* Save return address */
  86         move            t3, ra
  87
  88         /* Run from cacheable space now */
  89         bal             cachehere
  90         nop
  91 cachehere:
  92         li              t1, ~0x20000000 /* convert to KSEG0 */
  93         and             t0, ra, t1
  94         addi    t0, 5*4                 /* 5 insns beyond cachehere */
  95         jr              t0
  96         nop
  97
  98         /* Restore return address */
  99         move            ra, t3
 100
 101         /*
 102          * Step 9) Initialize the TLB
 103          */
 104         li              t0, 0                   # index value
 105         li              t1, 0x00000000          # entryhi value
 106         li              t2, 32                  # 32 entries
 107
 108 tlbloop:
 109         /* Probe TLB for matching EntryHi */
 110         mtc0    t1, CP0_ENTRYHI
 111         tlbp
 112         nop
 113
 114         /* Examine Index[P], 1=no matching entry */
 115         mfc0    t3, CP0_INDEX
 116         li      t4, 0x80000000
 117         and     t3, t4, t3
 118         addiu   t1, t1, 1               # increment t1 (asid)
 119         beq     zero, t3, tlbloop
 120         nop
 121
 122         /* Initialize the TLB entry */
 123         mtc0    t0, CP0_INDEX
 124         mtc0    zero, CP0_ENTRYLO0
 125         mtc0    zero, CP0_ENTRYLO1
 126         mtc0    zero, CP0_PAGEMASK
 127         tlbwi
 128
 129         /* Do it again */
 130         addiu   t0, t0, 1
 131         bne     t0, t2, tlbloop
 132         nop
 133
 134         /* First setup pll:s to make serial work ok */
 135         /* We have a 12.5 MHz crystal */
 136         li      t0, SYS_CPUPLL
 137         li      t1, 0x28  /* CPU clock, 500 MHz */
 138         sw      t1, 0(t0)
 139         sync
 140         nop
 141         nop
 142
 143         /* wait 1mS for clocks to settle */
 144         li      t1, MEM_1MS
 145 1:      add     t1, -1
 146         bne     t1, zero, 1b
 147         nop
 148         /* Setup AUX PLL */
 149         li      t0, SYS_AUXPLL
 150         li      t1, 0
 151         sw      t1, 0(t0) /* aux pll */
 152         sync
 153
 154         /*  Static memory controller */
 155         /* RCE0 - can not change while fetching, do so from icache */
 156         move            t2, ra /* Store return address */
 157         bal             getAddr
 158         nop
 159
 160 getAddr:
 161         move            t1, ra
 162         move            ra, t2 /* Move return addess back */
 163
 164         cache   0x14,0(t1)
 165         cache   0x14,32(t1)
 166         /*** /From YAMON ***/
 167
 168 noCacheJump:
 169
 170         /*  Static memory controller */
 171
 172         /* RCE0 AMD 29LV800 Flash */
 173         li      t0, MEM_STCFG0
 174         li      t1, 0x00000243
 175         sw      t1, 0(t0)
 176
 177         li      t0, MEM_STTIME0
 178         li      t1, 0x040181D7 /* FIXME */
 179         sw      t1, 0(t0)
 180
 181         li      t0, MEM_STADDR0
 182         li      t1, 0x11E03F80
 183         sw      t1, 0(t0)
 184
 185         /* RCE1 PCMCIA 250ns */
 186         li      t0, MEM_STCFG1
 187         li      t1, 0x00000002
 188         sw      t1, 0(t0)
 189
 190         li      t0, MEM_STTIME1
 191         li      t1, 0x280E3E07
 192         sw      t1, 0(t0)
 193
 194         li      t0, MEM_STADDR1
 195         li      t1, 0x10000000
 196         sw      t1, 0(t0)
 197
 198         /* RCE2 CP Altera */
 199         li      t0, MEM_STCFG2
 200         li      t1, 0x00000280 /* BE, EW */
 201         sw      t1, 0(t0)
 202
 203         li      t0, MEM_STTIME2
 204         li      t1, 0x0303000c
 205         sw      t1, 0(t0)
 206
 207         li      t0, MEM_STADDR2
 208         li      t1, 0x10c03f80 /* 1 MB */
 209         sw      t1, 0(t0)
 210
 211         /* RCE3 DP Altera */
 212         li      t0, MEM_STCFG3
 213         li      t1, 0x00000280 /* BE, EW */
 214         sw      t1, 0(t0)
 215
 216         li      t0, MEM_STTIME3
 217         li      t1, 0x0303000c
 218         sw      t1, 0(t0)
 219
 220         li      t0, MEM_STADDR3
 221         li      t1, 0x10e03f80 /* 1 MB */
 222         sw      t1, 0(t0)
 223
 224         sync
 225
 226         /* Set peripherals to a known state */
 227         li      t0, IC0_CFG0CLR
 228         li      t1, 0xFFFFFFFF
 229         sw      t1, 0(t0)
 230
 231         li      t0, IC0_CFG0CLR
 232         sw      t1, 0(t0)
 233
 234         li      t0, IC0_CFG1CLR
 235         sw      t1, 0(t0)
 236
 237         li      t0, IC0_CFG2CLR
 238         sw      t1, 0(t0)
 239
 240         li      t0, IC0_SRCSET
 241         sw      t1, 0(t0)
 242
 243         li      t0, IC0_ASSIGNSET
 244         sw      t1, 0(t0)
 245
 246         li      t0, IC0_WAKECLR
 247         sw      t1, 0(t0)
 248
 249         li      t0, IC0_RISINGCLR
 250         sw      t1, 0(t0)
 251
 252         li      t0, IC0_FALLINGCLR
 253         sw      t1, 0(t0)
 254
 255         li      t0, IC0_TESTBIT
 256         li      t1, 0x00000000
 257         sw      t1, 0(t0)
 258         sync
 259
 260         li      t0, IC1_CFG0CLR
 261         li      t1, 0xFFFFFFFF
 262         sw      t1, 0(t0)
 263
 264         li      t0, IC1_CFG0CLR
 265         sw      t1, 0(t0)
 266
 267         li      t0, IC1_CFG1CLR
 268         sw      t1, 0(t0)
 269
 270         li      t0, IC1_CFG2CLR
 271         sw      t1, 0(t0)
 272
 273         li      t0, IC1_SRCSET
 274         sw      t1, 0(t0)
 275
 276         li      t0, IC1_ASSIGNSET
 277         sw      t1, 0(t0)
 278
 279         li      t0, IC1_WAKECLR
 280         sw      t1, 0(t0)
 281
 282         li      t0, IC1_RISINGCLR
 283         sw      t1, 0(t0)
 284
 285         li      t0, IC1_FALLINGCLR
 286         sw      t1, 0(t0)
 287
 288         li      t0, IC1_TESTBIT
 289         li      t1, 0x00000000
 290         sw      t1, 0(t0)
 291         sync
 292
 293         li      t0, SYS_FREQCTRL0
 294         li      t1, 0x00000000
 295         sw      t1, 0(t0)
 296
 297         li      t0, SYS_FREQCTRL1
 298         li      t1, 0x00000000
 299         sw      t1, 0(t0)
 300
 301         li      t0, SYS_CLKSRC
 302         li      t1, 0x00000000
 303         sw      t1, 0(t0)
 304
 305         li      t0, SYS_PININPUTEN
 306         li      t1, 0x00000000
 307         sw      t1, 0(t0)
 308         sync
 309
 310         li      t0, 0xB1100100
 311         li      t1, 0x00000000
 312         sw      t1, 0(t0)
 313
 314         li      t0, 0xB1400100
 315         li      t1, 0x00000000
 316         sw      t1, 0(t0)
 317
 318
 319         li      t0, SYS_WAKEMSK
 320         li      t1, 0x00000000
 321         sw      t1, 0(t0)
 322
 323         li      t0, SYS_WAKESRC
 324         li      t1, 0x00000000
 325         sw      t1, 0(t0)
 326
 327         /* wait 1mS before setup */
 328         li      t1, MEM_1MS
 329 1:      add     t1, -1
 330         bne     t1, zero, 1b
 331         nop
 332
 333
 334 /* SDCS 0 SDRAM */
 335         li      t0, MEM_SDMODE0
 336         li      t1, 0x592CD1
 337         sw      t1, 0(t0)
 338
 339         li      t0, MEM_SDMODE1
 340         li      t1, 0x00000000
 341         sw      t1, 0(t0)
 342
 343         li      t0, MEM_SDMODE2
 344         li      t1, 0x00000000
 345         sw      t1, 0(t0)
 346
 347 /* 64 MB SDRAM at addr 0 */
 348         li      t0, MEM_SDADDR0
 349         li      t1, 0x001003F0
 350         sw      t1, 0(t0)
 351
 352
 353         li      t0, MEM_SDADDR1
 354         li      t1, 0x00000000
 355         sw      t1, 0(t0)
 356
 357         li      t0, MEM_SDADDR2
 358         li      t1, 0x00000000
 359         sw      t1, 0(t0)
 360
 361         sync
 362
 363         li      t0, MEM_SDREFCFG
 364         li      t1, 0x880007A1 /* Disable */
 365         sw      t1, 0(t0)
 366         sync
 367
 368         li      t0, MEM_SDPRECMD
 369         sw      zero, 0(t0)
 370         sync
 371
 372         li      t0, MEM_SDAUTOREF
 373         sw      zero, 0(t0)
 374         sync
 375         sw      zero, 0(t0)
 376         sync
 377
 378         li      t0, MEM_SDREFCFG
 379         li      t1, 0x8A0007A1 /* Enable */
 380         sw      t1, 0(t0)
 381         sync
 382
 383         li      t0, MEM_SDWRMD0
 384         li      t1, 0x00000023
 385         sw      t1, 0(t0)
 386         sync
 387
 388         /* wait 1mS after setup */
 389         li      t1, MEM_1MS
 390 1:      add     t1, -1
 391         bne     t1, zero, 1b
 392         nop
 393
 394         /* Setup GPIO pins */
 395
 396         li      t0, SYS_PINFUNC
 397         li      t1, 0x00007025 /* 0x8080 */
 398         sw      t1, 0(t0)
 399
 400         li      t0, SYS_TRIOUTCLR
 401         li      t1, 0xFFFFFFFF /* 0x1FFF */
 402         sw      t1, 0(t0)
 403
 404         /* Turn yellow front led on */
 405         /* Release reset on CF */
 406         li      t0, SYS_OUTPUTCLR
 407         li      t1, GPIO_RJ1LG
 408         sw      t1, 0(t0)
 409         li      t0, SYS_OUTPUTSET
 410         li      t1, GPIO_RJ1LY|GPIO_CFRESET
 411         sw      t1, 0(t0)
 412         sync
 413         j clearmem
 414         nop
 415
 416         .globl  memtest
 417 memtest:
 418         /* Fill memory with address */
 419         li      t0, 0x80000000
 420         li      t1, 0xFFF000 /* 64 MB */
 421 mt0:    sw      t0, 0(t0)
 422         add     t1, -1
 423         add     t0, 4
 424         bne     t1, zero, mt0
 425         nop
 426         nop
 427         /* Verify addr */
 428         li      t0, 0x80000000
 429         li      t1, 0xFFF000 /* 64 MB */
 430 mt1:    lw      t2, 0(t0)
 431         bne     t0, t2, memhang
 432         add     t1, -1
 433         add     t0, 4
 434         bne     t1, zero, mt1
 435         nop
 436         nop
 437         .globl  clearmem
 438 clearmem:
 439                 /* Clear memory */
 440         li      t0, 0x80000000
 441         li      t1, 0xFFF000 /* 64 MB */
 442 mtc:    sw      zero, 0(t0)
 443         add     t1, -1
 444         add     t0, 4
 445         bne     t1, zero, mtc
 446         nop
 447         nop
 448 memtestend:
 449         j       ra
 450         nop
 451
 452 memhang:
 453         b       memhang
 454         nop