1 // SPDX-License-Identifier: GPL-2.0+
4 * Gumstix Inc. <www.gumstix.com>
5 * Maintainer: Ash Charles <ash@gumstix.com>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/arch/mmc_host_def.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/gpio.h>
16 #include <asm/mach-types.h>
18 #include "duovero_mux_data.h"
22 #if defined(CONFIG_CMD_NET)
23 #define SMSC_NRESET 45
24 static void setup_net_chip(void);
27 #ifdef CONFIG_USB_EHCI_HCD
29 #include <asm/arch/ehci.h>
30 #include <asm/ehci-omap.h>
33 DECLARE_GLOBAL_DATA_PTR
;
35 const struct omap_sysinfo sysinfo
= {
39 struct omap4_scrm_regs
*const scrm
= (struct omap4_scrm_regs
*)0x4a30a000;
50 gd
->bd
->bi_arch_number
= MACH_TYPE_DUOVERO
;
51 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
57 * @brief misc_init_r - Configure board specific configurations
58 * such as power configurations, ethernet initialization as phase2 of
68 /* wifi setup: first enable 32Khz clock from 6030 pmic */
70 ret
= i2c_write(TWL6030_CHIP_PM
, 0xbe, 1, &val
, 1);
72 printf("Failed to enable 32Khz clock to wifi module\n");
74 /* then setup WIFI_EN as an output pin and send reset pulse */
75 if (!gpio_request(WIFI_EN
, "")) {
76 gpio_direction_output(WIFI_EN
, 0);
77 gpio_set_value(WIFI_EN
, 1);
79 gpio_set_value(WIFI_EN
, 0);
81 gpio_set_value(WIFI_EN
, 1);
84 #if defined(CONFIG_CMD_NET)
90 void set_muxconf_regs(void)
92 do_set_mux((*ctrl
)->control_padconf_core_base
,
93 core_padconf_array_essential
,
94 sizeof(core_padconf_array_essential
) /
95 sizeof(struct pad_conf_entry
));
97 do_set_mux((*ctrl
)->control_padconf_wkup_base
,
98 wkup_padconf_array_essential
,
99 sizeof(wkup_padconf_array_essential
) /
100 sizeof(struct pad_conf_entry
));
102 do_set_mux((*ctrl
)->control_padconf_core_base
,
103 core_padconf_array_non_essential
,
104 sizeof(core_padconf_array_non_essential
) /
105 sizeof(struct pad_conf_entry
));
107 do_set_mux((*ctrl
)->control_padconf_wkup_base
,
108 wkup_padconf_array_non_essential
,
109 sizeof(wkup_padconf_array_non_essential
) /
110 sizeof(struct pad_conf_entry
));
113 #if defined(CONFIG_MMC)
114 int board_mmc_init(bd_t
*bis
)
116 return omap_mmc_init(0, 0, 0, -1, -1);
119 #if !defined(CONFIG_SPL_BUILD)
120 void board_mmc_power_init(void)
122 twl6030_power_mmc_init(0);
127 #if defined(CONFIG_CMD_NET)
129 #define GPMC_SIZE_16M 0xF
130 #define GPMC_BASEADDR_MASK 0x3F
131 #define GPMC_CS_ENABLE 0x1
133 static void enable_gpmc_net_config(const u32
*gpmc_config
, const struct gpmc_cs
*cs
,
136 writel(0, &cs
->config7
);
138 /* Delay for settling */
139 writel(gpmc_config
[0], &cs
->config1
);
140 writel(gpmc_config
[1], &cs
->config2
);
141 writel(gpmc_config
[2], &cs
->config3
);
142 writel(gpmc_config
[3], &cs
->config4
);
143 writel(gpmc_config
[4], &cs
->config5
);
144 writel(gpmc_config
[5], &cs
->config6
);
147 * Enable the config. size is the CS size and goes in
148 * bits 11:8. We set bit 6 to enable this CS and the base
149 * address goes into bits 5:0.
151 writel((size
<< 8) | (GPMC_CS_ENABLE
<< 6) |
152 ((base
>> 24) & GPMC_BASEADDR_MASK
),
158 /* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
159 #define NET_LAN9221_GPMC_CONFIG1 0x2a001203
160 #define NET_LAN9221_GPMC_CONFIG2 0x000a0a02
161 #define NET_LAN9221_GPMC_CONFIG3 0x00020200
162 #define NET_LAN9221_GPMC_CONFIG4 0x0a030a03
163 #define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a
164 #define NET_LAN9221_GPMC_CONFIG6 0x8a070707
165 #define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
167 /* GPMC definitions for LAN9221 chips on expansion boards */
168 static const u32 gpmc_lan_config
[] = {
169 NET_LAN9221_GPMC_CONFIG1
,
170 NET_LAN9221_GPMC_CONFIG2
,
171 NET_LAN9221_GPMC_CONFIG3
,
172 NET_LAN9221_GPMC_CONFIG4
,
173 NET_LAN9221_GPMC_CONFIG5
,
174 NET_LAN9221_GPMC_CONFIG6
,
175 /*CONFIG7- computed as params */
179 * Routine: setup_net_chip
180 * Description: Setting up the configuration GPMC registers specific to the
183 static void setup_net_chip(void)
185 enable_gpmc_net_config(gpmc_lan_config
, &gpmc_cfg
->cs
[5], 0x2C000000,
188 /* Make GPIO SMSC_NRESET as output pin and send reset pulse */
189 if (!gpio_request(SMSC_NRESET
, "")) {
190 gpio_direction_output(SMSC_NRESET
, 0);
191 gpio_set_value(SMSC_NRESET
, 1);
193 gpio_set_value(SMSC_NRESET
, 0);
195 gpio_set_value(SMSC_NRESET
, 1);
200 int board_eth_init(bd_t
*bis
)
203 #ifdef CONFIG_SMC911X
204 rc
= smc911x_initialize(0, CONFIG_SMC911X_BASE
);
209 #ifdef CONFIG_USB_EHCI_HCD
211 static struct omap_usbhs_board_data usbhs_bdata
= {
212 .port_mode
[0] = OMAP_EHCI_PORT_MODE_PHY
,
213 .port_mode
[1] = OMAP_USBHS_PORT_MODE_UNUSED
,
214 .port_mode
[2] = OMAP_USBHS_PORT_MODE_UNUSED
,
217 int ehci_hcd_init(int index
, enum usb_init_type init
,
218 struct ehci_hccr
**hccr
, struct ehci_hcor
**hcor
)
221 unsigned int utmi_clk
;
222 u32 auxclk
, altclksrc
;
224 /* Now we can enable our port clocks */
225 utmi_clk
= readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL
);
226 utmi_clk
|= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK
;
227 setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL
, utmi_clk
);
229 auxclk
= readl(&scrm
->auxclk3
);
231 auxclk
&= ~AUXCLK_SRCSELECT_MASK
;
232 auxclk
|= AUXCLK_SRCSELECT_SYS_CLK
<< AUXCLK_SRCSELECT_SHIFT
;
233 /* Set the divisor to 2 */
234 auxclk
&= ~AUXCLK_CLKDIV_MASK
;
235 auxclk
|= AUXCLK_CLKDIV_2
<< AUXCLK_CLKDIV_SHIFT
;
236 /* Request auxilary clock #3 */
237 auxclk
|= AUXCLK_ENABLE_MASK
;
238 writel(auxclk
, &scrm
->auxclk3
);
240 altclksrc
= readl(&scrm
->altclksrc
);
242 /* Activate alternate system clock supplier */
243 altclksrc
&= ~ALTCLKSRC_MODE_MASK
;
244 altclksrc
|= ALTCLKSRC_MODE_ACTIVE
;
247 altclksrc
|= ALTCLKSRC_ENABLE_INT_MASK
| ALTCLKSRC_ENABLE_EXT_MASK
;
249 writel(altclksrc
, &scrm
->altclksrc
);
251 ret
= omap_ehci_hcd_init(index
, &usbhs_bdata
, hccr
, hcor
);
258 int ehci_hcd_stop(int index
)
260 return omap_ehci_hcd_stop();
265 * get_board_rev() - get board revision
267 u32
get_board_rev(void)