1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2017 Linaro
4 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
12 #include <dm/platform_data/serial_pl01x.h>
13 #include <asm/arch/hi3798cv200.h>
14 #include <asm/armv8/mmu.h>
16 DECLARE_GLOBAL_DATA_PTR
;
18 static struct mm_region poplar_mem_map
[] = {
23 .attrs
= PTE_BLOCK_MEMTYPE(MT_NORMAL
) |
29 .attrs
= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE
) |
31 PTE_BLOCK_PXN
| PTE_BLOCK_UXN
37 struct mm_region
*mem_map
= poplar_mem_map
;
39 #if !CONFIG_IS_ENABLED(OF_CONTROL)
40 static const struct pl01x_serial_platdata serial_platdata
= {
41 .base
= REG_BASE_UART0
,
46 U_BOOT_DEVICE(poplar_serial
) = {
47 .name
= "serial_pl01x",
48 .platdata
= &serial_platdata
,
54 puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
59 void reset_cpu(ulong addr
)
66 gd
->ram_size
= get_ram_size(NULL
, 0x80000000);
72 * Some linux kernel versions don't use memory before its load address, so to
73 * be generic we just pretend it isn't there. In previous uboot versions we
74 * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
75 * could persist in memory and be left alone by the kernel.
77 * That led to a problem when mapping memory in older kernels. That PSCI code
78 * now lies in memory below the kernel load offset; it therefore won't be
79 * touched by the kernel, and by not specially reserving it we avoid the mapping
83 #define KERNEL_TEXT_OFFSET 0x00080000
85 int dram_init_banksize(void)
87 gd
->bd
->bi_dram
[0].start
= KERNEL_TEXT_OFFSET
;
88 gd
->bd
->bi_dram
[0].size
= gd
->ram_size
- gd
->bd
->bi_dram
[0].start
;
93 static void usb2_phy_config(void)
95 const u32 config
[] = {
96 /* close EOP pre-emphasis. open data pre-emphasis */
98 /* Rcomp = 150mW, increase DC level */
100 /* keep Rcomp working */
102 /* Icomp = 212mW, increase current drive */
104 /* EMI fix: rx_active not stay 1 when error packets received */
106 /* Comp mode select */
108 /* adjust eye diagram */
110 /* adjust eye diagram */
115 for (i
= 0; i
< ARRAY_SIZE(config
); i
++) {
116 writel(config
[i
], PERI_CTRL_USB0
);
117 clrsetbits_le32(PERI_CTRL_USB0
, BIT(21), BIT(20) | BIT(22));
122 static void usb2_phy_init(void)
124 /* reset usb2 controller bus/utmi/roothub */
125 setbits_le32(PERI_CRG46
, USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ
|
126 USB2_HST_PHY_SYST_REQ
| USB2_OTG_PHY_SYST_REQ
);
129 /* reset usb2 phy por/utmi */
130 setbits_le32(PERI_CRG47
, USB2_PHY01_SRST_REQ
| USB2_PHY01_SRST_TREQ1
);
133 /* open usb2 ref clk */
134 setbits_le32(PERI_CRG47
, USB2_PHY01_REF_CKEN
);
137 /* cancel usb2 power on reset */
138 clrbits_le32(PERI_CRG47
, USB2_PHY01_SRST_REQ
);
143 /* cancel usb2 port reset, wait comp circuit stable */
144 clrbits_le32(PERI_CRG47
, USB2_PHY01_SRST_TREQ1
);
147 /* open usb2 controller clk */
148 setbits_le32(PERI_CRG46
, USB2_BUS_CKEN
| USB2_OHCI48M_CKEN
|
149 USB2_OHCI12M_CKEN
| USB2_OTG_UTMI_CKEN
|
150 USB2_HST_PHY_CKEN
| USB2_UTMI0_CKEN
);
153 /* cancel usb2 control reset */
154 clrbits_le32(PERI_CRG46
, USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ
|
155 USB2_HST_PHY_SYST_REQ
| USB2_OTG_PHY_SYST_REQ
);
159 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
162 #include <usb/dwc2_udc.h>
165 static struct dwc2_plat_otg_data poplar_otg_data
= {
166 .regs_otg
= HIOTG_BASE_ADDR
169 static void set_usb_to_device(void)
171 setbits_le32(PERI_CTRL_USB3
, USB2_2P_CHIPID
);
174 int board_usb_init(int index
, enum usb_init_type init
)
177 return dwc2_udc_probe(&poplar_otg_data
);
180 int g_dnl_bind_fixup(struct usb_device_descriptor
*dev
, const char *name
)
182 if (!env_get("serial#"))
183 g_dnl_set_serialnumber("0123456789POPLAR");