3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * hacked for Hymod FPGA support by Murray.Jensen@csiro.au, 29-Jan-01
29 #include <asm/iopin_8260.h>
31 DECLARE_GLOBAL_DATA_PTR
;
33 /*-----------------------------------------------------------------------
34 * Board Special Commands: FPGA load/store, EEPROM erase
37 #if defined(CONFIG_CMD_BSP)
39 #define LOAD_SUCCESS 0
40 #define LOAD_FAIL_NOCONF 1
41 #define LOAD_FAIL_NOINIT 2
42 #define LOAD_FAIL_NODONE 3
44 #define STORE_SUCCESS 0
47 * Programming the Hymod FPGAs
49 * The 8260 io port config table is set up so that the INIT pin is
50 * held Low (Open Drain output 0) - this will delay the automatic
51 * Power-On config until INIT is released (by making it an input).
53 * If the FPGA has been programmed before, then the assertion of PROGRAM
54 * will initiate configuration (i.e. it begins clearing the RAM).
56 * When the FPGA is ready to receive configuration data (either after
57 * releasing INIT after Power-On, or after asserting PROGRAM), it will
60 * Notes from Paul Dunn:
62 * 1. program pin should be forced low for >= 300ns
63 * (about 20 bus clock cycles minimum).
65 * 2. then wait for init to go high, which signals
66 * that the FPGA has cleared its internal memory
67 * and is ready to load
69 * 3. perform load writes of entire config file
71 * 4. wait for done to go high, which should be
72 * within a few bus clock cycles. If done has not
73 * gone high after reasonable period, then load
74 * has not worked (wait several ms?)
78 fpga_load (int mezz
, uchar
*addr
, ulong size
)
80 hymod_conf_t
*cp
= &gd
->bd
->bi_hymod_conf
;
83 volatile uchar
*fpgabase
;
85 uchar
*eaddr
= addr
+ size
;
89 fp
= &cp
->mezz
.xlx
[0];
91 fp
= &cp
->main
.xlx
[0];
93 if (!fp
->mmap
.prog
.exists
)
94 return (LOAD_FAIL_NOCONF
);
96 fpgabase
= (uchar
*)fp
->mmap
.prog
.base
;
99 /* set enable HIGH if required */
100 if (fpgaio
->enable_pin
.flag
)
101 iopin_set_high (&fpgaio
->enable_pin
);
103 /* ensure INIT is released (set it to be an input) */
104 iopin_set_in (&fpgaio
->init_pin
);
106 /* toggle PROG Low then High (will already be Low after Power-On) */
107 iopin_set_low (&fpgaio
->prog_pin
);
108 udelay (1); /* minimum 300ns - 1usec should do it */
109 iopin_set_high (&fpgaio
->prog_pin
);
111 /* wait for INIT High */
113 while (!iopin_is_high (&fpgaio
->init_pin
))
114 if (++cnt
== 10000000) {
115 result
= LOAD_FAIL_NOINIT
;
119 /* write configuration data */
123 /* wait for DONE High */
125 while (!iopin_is_high (&fpgaio
->done_pin
))
126 if (++cnt
== 100000000) {
127 result
= LOAD_FAIL_NODONE
;
132 result
= LOAD_SUCCESS
;
136 if (fpgaio
->enable_pin
.flag
)
137 iopin_set_low (&fpgaio
->enable_pin
);
142 /* ------------------------------------------------------------------------- */
144 do_fpga (cmd_tbl_t
* cmdtp
, int flag
, int argc
, char *argv
[])
146 uchar
*addr
, *save_addr
;
148 int mezz
, arg
, result
;
157 if (strcmp (argv
[1], "info") == 0) {
158 printf ("\nHymod FPGA Info...\n");
159 printf ("\t\t\t\tAddress\t\tSize\n");
160 printf ("\tMain Configuration:\t0x%08x\t%d\n",
161 FPGA_MAIN_CFG_BASE
, FPGA_MAIN_CFG_SIZE
);
162 printf ("\tMain Register:\t\t0x%08x\t%d\n",
163 FPGA_MAIN_REG_BASE
, FPGA_MAIN_REG_SIZE
);
164 printf ("\tMain Port:\t\t0x%08x\t%d\n",
165 FPGA_MAIN_PORT_BASE
, FPGA_MAIN_PORT_SIZE
);
166 printf ("\tMezz Configuration:\t0x%08x\t%d\n",
167 FPGA_MEZZ_CFG_BASE
, FPGA_MEZZ_CFG_SIZE
);
173 if (strcmp (argv
[1], "store") == 0) {
174 addr
= (uchar
*) simple_strtoul (argv
[2], NULL
, 16);
178 /* fpga readback unimplemented */
179 while (more readback data
)
181 result
= error
? STORE_FAIL_XXX
: STORE_SUCCESS
;
183 result
= STORE_SUCCESS
;
186 if (result
== STORE_SUCCESS
) {
187 printf ("SUCCEEDED (%d bytes)\n",
191 printf ("FAILED (%d bytes)\n",
198 if (strcmp (argv
[1], "tftp") == 0) {
199 copy_filename (BootFile
, argv
[2], sizeof (BootFile
));
200 load_addr
= simple_strtoul (argv
[3], NULL
, 16);
201 NetBootFileXferSize
= 0;
203 if (NetLoop (TFTP
) <= 0) {
204 printf ("tftp transfer failed - aborting "
209 if (NetBootFileXferSize
== 0) {
210 printf ("can't determine file size - "
211 "aborting fpga load\n");
215 printf ("File transfer succeeded - "
216 "beginning fpga load...");
218 result
= fpga_load (0, (uchar
*) load_addr
,
219 NetBootFileXferSize
);
221 if (result
== LOAD_SUCCESS
) {
222 printf ("SUCCEEDED\n");
224 } else if (result
== LOAD_FAIL_NOCONF
)
225 printf ("FAILED (no CONF)\n");
226 else if (result
== LOAD_FAIL_NOINIT
)
227 printf ("FAILED (no INIT)\n");
229 printf ("FAILED (no DONE)\n");
233 /* fall through ... */
236 if (strcmp (argv
[1], "load") == 0) {
238 if (strcmp (argv
[2], "main") == 0)
240 else if (strcmp (argv
[2], "mezz") == 0)
243 printf ("FPGA type must be either "
244 "`main' or `mezz'\n");
253 addr
= (uchar
*) simple_strtoul (argv
[arg
++], NULL
, 16);
254 size
= (ulong
) simple_strtoul (argv
[arg
], NULL
, 16);
256 result
= fpga_load (mezz
, addr
, size
);
258 if (result
== LOAD_SUCCESS
) {
259 printf ("SUCCEEDED\n");
261 } else if (result
== LOAD_FAIL_NOCONF
)
262 printf ("FAILED (no CONF)\n");
263 else if (result
== LOAD_FAIL_NOINIT
)
264 printf ("FAILED (no INIT)\n");
266 printf ("FAILED (no DONE)\n");
281 "load [type] addr size\n"
282 " - write the configuration data at memory address `addr',\n"
283 " size `size' bytes, into the FPGA of type `type' (either\n"
284 " `main' or `mezz', default `main'). e.g.\n"
285 " `fpga load 100000 7d8f'\n"
286 " loads the main FPGA with config data at address 100000\n"
287 " HEX, size 7d8f HEX (32143 DEC) bytes\n"
288 "fpga tftp file addr\n"
289 " - transfers `file' from the tftp server into memory at\n"
290 " address `addr', then writes the entire file contents\n"
291 " into the main FPGA\n"
293 " - read configuration data from the main FPGA (the mezz\n"
294 " FPGA is write-only), into address `addr'. There must be\n"
295 " enough memory available at `addr' to hold all the config\n"
296 " data - the size of which is determined by VC:???\n"
298 " - print information about the Hymod FPGA, namely the\n"
299 " memory addresses at which the four FPGA local bus\n"
300 " address spaces appear in the physical address space\n"
302 /* ------------------------------------------------------------------------- */
304 do_eecl (cmd_tbl_t
* cmdtp
, int flag
, int argc
, char *argv
[])
306 uchar data
[HYMOD_EEPROM_SIZE
];
307 uint addr
= CONFIG_SYS_I2C_EEPROM_ADDR
;
312 addr
|= HYMOD_EEOFF_MAIN
;
316 if (strcmp (argv
[1], "main") == 0) {
317 addr
|= HYMOD_EEOFF_MAIN
;
320 if (strcmp (argv
[1], "mezz") == 0) {
321 addr
|= HYMOD_EEOFF_MEZZ
;
324 /* fall through ... */
331 memset (data
, 0, HYMOD_EEPROM_SIZE
);
333 eeprom_write (addr
, 0, data
, HYMOD_EEPROM_SIZE
);
338 eeclear
, 1, 0, do_eecl
,
339 "Clear the eeprom on a Hymod board",
341 " - write zeroes into the EEPROM on the board of type `type'\n"
342 " (`type' is either `main' or `mezz' - default `main')\n"
343 " Note: the EEPROM write enable jumper must be installed\n"
346 /* ------------------------------------------------------------------------- */
349 do_htest (cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *argv
[])
354 #ifdef CONFIG_ETHER_LOOPBACK_TEST
355 extern void eth_loopback_test (void);
356 #endif /* CONFIG_ETHER_LOOPBACK_TEST */
358 printf ("HYMOD tests - ensure loopbacks etc. are connected\n\n");
361 /* Load FPGA with test program */
363 printf ("Loading test FPGA program ...");
365 rc
= fpga_load (0, test_bitfile
, sizeof (test_bitfile
));
370 printf (" SUCCEEDED\n");
373 case LOAD_FAIL_NOCONF
:
374 printf (" FAILED (no configuration space defined)\n");
377 case LOAD_FAIL_NOINIT
:
378 printf (" FAILED (timeout - no INIT signal seen)\n");
381 case LOAD_FAIL_NODONE
:
382 printf (" FAILED (timeout - no DONE signal seen)\n");
386 printf (" FAILED (unknown return code from fpga_load\n");
390 /* run Local Bus <=> Xilinx tests */
392 /* tell Xilinx to run ZBT Ram, High Speed serial and Mezzanine tests */
397 #ifdef CONFIG_ETHER_LOOPBACK_TEST
398 /* run Ethernet test */
399 eth_loopback_test ();
400 #endif /* CONFIG_ETHER_LOOPBACK_TEST */