board/icecube/icecube.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc5xxx.h>
  29 #include <pci.h>
  30
  31 #if defined(CONFIG_MPC5200_DDR)
  32 #include "mt46v16m16-75.h"
  33 #else
  34 #include "mt48lc16m16a2-75.h"
  35 #endif
  36
  37 #ifndef CFG_RAMBOOT
  38 static void sdram_start (int hi_addr)
  39 {
  40         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  41
  42         /* unlock mode register */
  43         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  44         __asm__ volatile ("sync");
  45
  46         /* precharge all banks */
  47         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  48         __asm__ volatile ("sync");
  49
  50 #if SDRAM_DDR
  51         /* set mode register: extended mode */
  52         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  53         __asm__ volatile ("sync");
  54
  55         /* set mode register: reset DLL */
  56         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  57         __asm__ volatile ("sync");
  58 #endif
  59
  60         /* precharge all banks */
  61         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  62         __asm__ volatile ("sync");
  63
  64         /* auto refresh */
  65         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  66         __asm__ volatile ("sync");
  67
  68         /* set mode register */
  69         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  70         __asm__ volatile ("sync");
  71
  72         /* normal operation */
  73         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  74         __asm__ volatile ("sync");
  75 }
  76 #endif
  77
  78 /*
  79  * ATTENTION: Although partially referenced initdram does NOT make real use
  80  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
  81  *            is something else than 0x00000000.
  82  */
  83
  84 #if defined(CONFIG_MPC5200)
  85 long int initdram (int board_type)
  86 {
  87         ulong dramsize = 0;
  88         ulong dramsize2 = 0;
  89 #ifndef CFG_RAMBOOT
  90         ulong test1, test2;
  91
  92         /* setup SDRAM chip selects */
  93         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  94         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
  95         __asm__ volatile ("sync");
  96
  97         /* setup config registers */
  98         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  99         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 100         __asm__ volatile ("sync");
 101
 102 #if SDRAM_DDR
 103         /* set tap delay */
 104         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 105         __asm__ volatile ("sync");
 106 #endif
 107
 108         /* find RAM size using SDRAM CS0 only */
 109         sdram_start(0);
 110         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 111         sdram_start(1);
 112         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 113         if (test1 > test2) {
 114                 sdram_start(0);
 115                 dramsize = test1;
 116         } else {
 117                 dramsize = test2;
 118         }
 119
 120         /* memory smaller than 1MB is impossible */
 121         if (dramsize < (1 << 20)) {
 122                 dramsize = 0;
 123         }
 124
 125         /* set SDRAM CS0 size according to the amount of RAM found */
 126         if (dramsize > 0) {
 127                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 128         } else {
 129                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 130         }
 131
 132         /* let SDRAM CS1 start right after CS0 */
 133         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 134
 135         /* find RAM size using SDRAM CS1 only */
 136         if (!dramsize)
 137                 sdram_start(0);
 138         test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 139         if (!dramsize) {
 140                 sdram_start(1);
 141                 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 142         }
 143         if (test1 > test2) {
 144                 sdram_start(0);
 145                 dramsize2 = test1;
 146         } else {
 147                 dramsize2 = test2;
 148         }
 149
 150         /* memory smaller than 1MB is impossible */
 151         if (dramsize2 < (1 << 20)) {
 152                 dramsize2 = 0;
 153         }
 154
 155         /* set SDRAM CS1 size according to the amount of RAM found */
 156         if (dramsize2 > 0) {
 157                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 158                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 159         } else {
 160                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 161         }
 162
 163 #else /* CFG_RAMBOOT */
 164
 165         /* retrieve size of memory connected to SDRAM CS0 */
 166         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 167         if (dramsize >= 0x13) {
 168                 dramsize = (1 << (dramsize - 0x13)) << 20;
 169         } else {
 170                 dramsize = 0;
 171         }
 172
 173         /* retrieve size of memory connected to SDRAM CS1 */
 174         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 175         if (dramsize2 >= 0x13) {
 176                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 177         } else {
 178                 dramsize2 = 0;
 179         }
 180
 181 #endif /* CFG_RAMBOOT */
 182
 183         return dramsize + dramsize2;
 184 }
 185
 186 #elif defined(CONFIG_MGT5100)
 187
 188 long int initdram (int board_type)
 189 {
 190         ulong dramsize = 0;
 191 #ifndef CFG_RAMBOOT
 192         ulong test1, test2;
 193
 194         /* setup and enable SDRAM chip selects */
 195         *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
 196         *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
 197         *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
 198         __asm__ volatile ("sync");
 199
 200         /* setup config registers */
 201         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 202         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 203
 204         /* address select register */
 205         *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
 206         __asm__ volatile ("sync");
 207
 208         /* find RAM size */
 209         sdram_start(0);
 210         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 211         sdram_start(1);
 212         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 213         if (test1 > test2) {
 214                 sdram_start(0);
 215                 dramsize = test1;
 216         } else {
 217                 dramsize = test2;
 218         }
 219
 220         /* set SDRAM end address according to size */
 221         *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 222
 223 #else /* CFG_RAMBOOT */
 224
 225         /* Retrieve amount of SDRAM available */
 226         dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 227
 228 #endif /* CFG_RAMBOOT */
 229
 230         return dramsize;
 231 }
 232
 233 #else
 234 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
 235 #endif
 236
 237 int checkboard (void)
 238 {
 239 #if defined(CONFIG_MPC5200)
 240         puts ("Board: Motorola MPC5200 (IceCube)\n");
 241 #elif defined(CONFIG_MGT5100)
 242         puts ("Board: Motorola MGT5100 (IceCube)\n");
 243 #endif
 244         return 0;
 245 }
 246
 247 void flash_preinit(void)
 248 {
 249         /*
 250          * Now, when we are in RAM, enable flash write
 251          * access for detection process.
 252          * Note that CS_BOOT cannot be cleared when
 253          * executing in flash.
 254          */
 255 #if defined(CONFIG_MGT5100)
 256         *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
 257         *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
 258 #endif
 259         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 260 }
 261
 262 void flash_afterinit(ulong size)
 263 {
 264         if (size == 0x800000) { /* adjust mapping */
 265                 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 266                         START_REG(CFG_BOOTCS_START | size);
 267                 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 268                         STOP_REG(CFG_BOOTCS_START | size, size);
 269         }
 270 }
 271
 272 #ifdef  CONFIG_PCI
 273 static struct pci_controller hose;
 274
 275 extern void pci_mpc5xxx_init(struct pci_controller *);
 276
 277 void pci_init_board(void)
 278 {
 279         pci_mpc5xxx_init(&hose);
 280 }
 281 #endif
 282
 283 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
 284
 285 #define GPIO_PSC1_4     0x01000000UL
 286
 287 void init_ide_reset (void)
 288 {
 289         debug ("init_ide_reset\n");
 290
 291         /* Configure PSC1_4 as GPIO output for ATA reset */
 292         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 293         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 294         /* Deassert reset */
 295         *(vu_long *) MPC5XXX_WU_GPIO_DATA   |= GPIO_PSC1_4;
 296 }
 297
 298 void ide_set_reset (int idereset)
 299 {
 300         debug ("ide_reset(%d)\n", idereset);
 301
 302         if (idereset) {
 303                 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
 304                 /* Make a delay. MPC5200 spec says 25 usec min */
 305                 udelay(500000);
 306         } else {
 307                 *(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
 308         }
 309 }
 310 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */