board/icecube/icecube.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc5xxx.h>
  29 #include <pci.h>
  30 #include <asm/processor.h>
  31 #include <libfdt.h>
  32
  33 #if defined(CONFIG_LITE5200B)
  34 #include "mt46v32m16.h"
  35 #else
  36 # if defined(CONFIG_MPC5200_DDR)
  37 #  include "mt46v16m16-75.h"
  38 # else
  39 #include "mt48lc16m16a2-75.h"
  40 # endif
  41 #endif
  42
  43 #ifdef CONFIG_LITE5200B_PM
  44 /* u-boot part of low-power mode implementation */
  45 #define SAVED_ADDR (*(void **)0x00000000)
  46 #define PSC2_4 0x02
  47
  48 void lite5200b_wakeup(void)
  49 {
  50         unsigned char wakeup_pin;
  51         void (*linux_wakeup)(void);
  52
  53         /* check PSC2_4, if it's down "QT" is signaling we have a wakeup
  54          * from low power mode */
  55         *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
  56         __asm__ volatile ("sync");
  57
  58         wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
  59         if (wakeup_pin & PSC2_4)
  60                 return;
  61
  62         /* acknowledge to "QT"
  63          * by holding pin at 1 for 10 uS */
  64         *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
  65         __asm__ volatile ("sync");
  66         *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
  67         __asm__ volatile ("sync");
  68         udelay(10);
  69
  70         /* put ram out of self-refresh */
  71         *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000;   /* mode_en */
  72         __asm__ volatile ("sync");
  73         *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000;   /* cke ref_en */
  74         __asm__ volatile ("sync");
  75         *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000;  /* !mode_en */
  76         __asm__ volatile ("sync");
  77         udelay(10); /* wait a bit */
  78
  79         /* jump back to linux kernel code */
  80         linux_wakeup = SAVED_ADDR;
  81         printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
  82                         linux_wakeup);
  83         linux_wakeup();
  84 }
  85 #else
  86 #define lite5200b_wakeup()
  87 #endif
  88
  89 #ifndef CFG_RAMBOOT
  90 static void sdram_start (int hi_addr)
  91 {
  92         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  93
  94         /* unlock mode register */
  95         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  96         __asm__ volatile ("sync");
  97
  98         /* precharge all banks */
  99         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
 100         __asm__ volatile ("sync");
 101
 102 #if SDRAM_DDR
 103         /* set mode register: extended mode */
 104         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
 105         __asm__ volatile ("sync");
 106
 107         /* set mode register: reset DLL */
 108         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
 109         __asm__ volatile ("sync");
 110 #endif
 111
 112         /* precharge all banks */
 113         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
 114         __asm__ volatile ("sync");
 115
 116         /* auto refresh */
 117         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
 118         __asm__ volatile ("sync");
 119
 120         /* set mode register */
 121         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
 122         __asm__ volatile ("sync");
 123
 124         /* normal operation */
 125         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
 126         __asm__ volatile ("sync");
 127 }
 128 #endif
 129
 130 /*
 131  * ATTENTION: Although partially referenced initdram does NOT make real use
 132  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
 133  *            is something else than 0x00000000.
 134  */
 135
 136 #if defined(CONFIG_MPC5200)
 137 long int initdram (int board_type)
 138 {
 139         ulong dramsize = 0;
 140         ulong dramsize2 = 0;
 141         uint svr, pvr;
 142
 143 #ifndef CFG_RAMBOOT
 144         ulong test1, test2;
 145
 146         /* setup SDRAM chip selects */
 147         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
 148         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
 149         __asm__ volatile ("sync");
 150
 151         /* setup config registers */
 152         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 153         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 154         __asm__ volatile ("sync");
 155
 156 #if SDRAM_DDR
 157         /* set tap delay */
 158         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 159         __asm__ volatile ("sync");
 160 #endif
 161
 162         /* find RAM size using SDRAM CS0 only */
 163         sdram_start(0);
 164         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 165         sdram_start(1);
 166         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 167         if (test1 > test2) {
 168                 sdram_start(0);
 169                 dramsize = test1;
 170         } else {
 171                 dramsize = test2;
 172         }
 173
 174         /* memory smaller than 1MB is impossible */
 175         if (dramsize < (1 << 20)) {
 176                 dramsize = 0;
 177         }
 178
 179         /* set SDRAM CS0 size according to the amount of RAM found */
 180         if (dramsize > 0) {
 181                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 182         } else {
 183                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 184         }
 185
 186         /* let SDRAM CS1 start right after CS0 */
 187         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 188
 189         /* find RAM size using SDRAM CS1 only */
 190         if (!dramsize)
 191                 sdram_start(0);
 192         test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 193         if (!dramsize) {
 194                 sdram_start(1);
 195                 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 196         }
 197         if (test1 > test2) {
 198                 sdram_start(0);
 199                 dramsize2 = test1;
 200         } else {
 201                 dramsize2 = test2;
 202         }
 203
 204         /* memory smaller than 1MB is impossible */
 205         if (dramsize2 < (1 << 20)) {
 206                 dramsize2 = 0;
 207         }
 208
 209         /* set SDRAM CS1 size according to the amount of RAM found */
 210         if (dramsize2 > 0) {
 211                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 212                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 213         } else {
 214                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 215         }
 216
 217 #else /* CFG_RAMBOOT */
 218
 219         /* retrieve size of memory connected to SDRAM CS0 */
 220         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 221         if (dramsize >= 0x13) {
 222                 dramsize = (1 << (dramsize - 0x13)) << 20;
 223         } else {
 224                 dramsize = 0;
 225         }
 226
 227         /* retrieve size of memory connected to SDRAM CS1 */
 228         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 229         if (dramsize2 >= 0x13) {
 230                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 231         } else {
 232                 dramsize2 = 0;
 233         }
 234
 235 #endif /* CFG_RAMBOOT */
 236
 237         /*
 238          * On MPC5200B we need to set the special configuration delay in the
 239          * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 240          * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 241          *
 242          * "The SDelay should be written to a value of 0x00000004. It is
 243          * required to account for changes caused by normal wafer processing
 244          * parameters."
 245          */
 246         svr = get_svr();
 247         pvr = get_pvr();
 248         if ((SVR_MJREV(svr) >= 2) &&
 249             (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
 250
 251                 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
 252                 __asm__ volatile ("sync");
 253         }
 254
 255         lite5200b_wakeup();
 256
 257         return dramsize + dramsize2;
 258 }
 259
 260 #elif defined(CONFIG_MGT5100)
 261
 262 long int initdram (int board_type)
 263 {
 264         ulong dramsize = 0;
 265 #ifndef CFG_RAMBOOT
 266         ulong test1, test2;
 267
 268         /* setup and enable SDRAM chip selects */
 269         *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
 270         *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
 271         *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
 272         __asm__ volatile ("sync");
 273
 274         /* setup config registers */
 275         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 276         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 277
 278         /* address select register */
 279         *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
 280         __asm__ volatile ("sync");
 281
 282         /* find RAM size */
 283         sdram_start(0);
 284         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 285         sdram_start(1);
 286         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 287         if (test1 > test2) {
 288                 sdram_start(0);
 289                 dramsize = test1;
 290         } else {
 291                 dramsize = test2;
 292         }
 293
 294         /* set SDRAM end address according to size */
 295         *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 296
 297 #else /* CFG_RAMBOOT */
 298
 299         /* Retrieve amount of SDRAM available */
 300         dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 301
 302 #endif /* CFG_RAMBOOT */
 303
 304         return dramsize;
 305 }
 306
 307 #else
 308 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
 309 #endif
 310
 311 int checkboard (void)
 312 {
 313 #if defined (CONFIG_LITE5200B)
 314         puts ("Board: Freescale Lite5200B\n");
 315 #elif defined(CONFIG_MPC5200)
 316         puts ("Board: Motorola MPC5200 (IceCube)\n");
 317 #elif defined(CONFIG_MGT5100)
 318         puts ("Board: Motorola MGT5100 (IceCube)\n");
 319 #endif
 320         return 0;
 321 }
 322
 323 void flash_preinit(void)
 324 {
 325         /*
 326          * Now, when we are in RAM, enable flash write
 327          * access for detection process.
 328          * Note that CS_BOOT cannot be cleared when
 329          * executing in flash.
 330          */
 331 #if defined(CONFIG_MGT5100)
 332         *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
 333         *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
 334 #endif
 335         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 336 }
 337
 338 void flash_afterinit(ulong size)
 339 {
 340         if (size == 0x800000) { /* adjust mapping */
 341                 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 342                         START_REG(CFG_BOOTCS_START | size);
 343                 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 344                         STOP_REG(CFG_BOOTCS_START | size, size);
 345         }
 346 }
 347
 348 #ifdef  CONFIG_PCI
 349 static struct pci_controller hose;
 350
 351 extern void pci_mpc5xxx_init(struct pci_controller *);
 352
 353 void pci_init_board(void)
 354 {
 355         pci_mpc5xxx_init(&hose);
 356 }
 357 #endif
 358
 359 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 360
 361 void init_ide_reset (void)
 362 {
 363         debug ("init_ide_reset\n");
 364
 365         /* Configure PSC1_4 as GPIO output for ATA reset */
 366         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 367         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 368         /* Deassert reset */
 369         *(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
 370 }
 371
 372 void ide_set_reset (int idereset)
 373 {
 374         debug ("ide_reset(%d)\n", idereset);
 375
 376         if (idereset) {
 377                 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
 378                 /* Make a delay. MPC5200 spec says 25 usec min */
 379                 udelay(500000);
 380         } else {
 381                 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
 382         }
 383 }
 384 #endif
 385
 386 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 387 void
 388 ft_board_setup(void *blob, bd_t *bd)
 389 {
 390         ft_cpu_setup(blob, bd);
 391 }
 392 #endif