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git.ipfire.org Git - people/ms/u-boot.git/blob - board/icecube/icecube.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 static void sdram_start (int hi_addr
)
31 long hi_addr_bit
= hi_addr
? 0x01000000 : 0;
33 #ifdef CONFIG_MPC5200_DDR
34 /* unlock mode register */
35 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= 0xf05f0f00 | hi_addr_bit
;
36 /* precharge all banks */
37 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= 0xf05f0f02 | hi_addr_bit
;
38 /* set mode register: extended mode */
39 *(vu_long
*)MPC5XXX_SDRAM_MODE
= 0x40090000;
40 /* set mode register: reset DLL */
41 *(vu_long
*)MPC5XXX_SDRAM_MODE
= 0x058d0000;
42 /* precharge all banks */
43 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= 0xf05f0f02 | hi_addr_bit
;
45 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= 0xf05f0f04 | hi_addr_bit
;
46 /* set mode register */
47 *(vu_long
*)MPC5XXX_SDRAM_MODE
= 0x018d0000;
48 /* normal operation */
49 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= 0x705f0f00 | hi_addr_bit
;
51 /* unlock mode register */
52 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= 0xd04f0000 | hi_addr_bit
;
53 /* precharge all banks */
54 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= 0xd04f0002 | hi_addr_bit
;
55 /* set mode register */
56 #if defined(CONFIG_MPC5200)
57 *(vu_long
*)MPC5XXX_SDRAM_MODE
= 0x00cd0000;
58 #elif defined(CONFIG_MGT5100)
59 *(vu_long
*)MPC5XXX_SDRAM_MODE
= 0x008d0000;
62 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= 0xd04f0004 | hi_addr_bit
;
64 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= 0xd04f0004 | hi_addr_bit
;
65 /* set mode register */
66 *(vu_long
*)MPC5XXX_SDRAM_MODE
= 0x00cd0000;
67 /* normal operation */
68 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= 0x504f0000 | hi_addr_bit
;
73 long int initdram (int board_type
)
76 #ifdef CONFIG_MPC5200_DDR
82 /* configure SDRAM start/end */
83 #if defined(CONFIG_MPC5200)
84 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0x0000001e;/* 2G at 0x0 */
85 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= 0x80000000;/* disabled */
87 #ifdef CONFIG_MPC5200_DDR
88 /* setup config registers */
89 *(vu_long
*)MPC5XXX_SDRAM_CONFIG1
= 0x73722930;
90 *(vu_long
*)MPC5XXX_SDRAM_CONFIG2
= 0x47770000;
92 /* set tap delay to 0x10 */
93 *(vu_long
*)MPC5XXX_CDM_PORCFG
= 0x10000000;
95 /* setup config registers */
96 *(vu_long
*)MPC5XXX_SDRAM_CONFIG1
= 0xd2322800;
97 *(vu_long
*)MPC5XXX_SDRAM_CONFIG2
= 0x8ad70000;
100 #elif defined(CONFIG_MGT5100)
101 *(vu_long
*)MPC5XXX_SDRAM_START
= 0x00000000;
102 *(vu_long
*)MPC5XXX_SDRAM_STOP
= 0x0000ffff;/* 2G */
103 *(vu_long
*)MPC5XXX_ADDECR
|= (1 << 22); /* Enable SDRAM */
105 /* setup config registers */
106 *(vu_long
*)MPC5XXX_SDRAM_CONFIG1
= 0xc2222600;
107 *(vu_long
*)MPC5XXX_SDRAM_CONFIG2
= 0x88b70004;
109 /* address select register */
110 *(vu_long
*)MPC5XXX_SDRAM_XLBSEL
= 0x03000000;
113 test1
= get_ram_size((ulong
*)CFG_SDRAM_BASE
, 0x80000000);
115 test2
= get_ram_size((ulong
*)CFG_SDRAM_BASE
, 0x80000000);
122 #if defined(CONFIG_MPC5200)
123 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
=
124 (0x13 + __builtin_ffs(dramsize
>> 20) - 1);
125 #ifdef CONFIG_MPC5200_DDR
126 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
+ 0x0000001e;/* 2G */
128 test1
= get_ram_size((ulong
*)(CFG_SDRAM_BASE
+ dramsize
), 0x80000000);
130 test2
= get_ram_size((ulong
*)(CFG_SDRAM_BASE
+ dramsize
), 0x80000000);
137 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
=
138 dramsize
+ (0x13 + __builtin_ffs(dramsize2
>> 20) - 1);
140 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
; /* disabled */
142 #elif defined(CONFIG_MGT5100)
143 *(vu_long
*)MPC5XXX_SDRAM_STOP
= ((dramsize
- 1) >> 15);
146 #else /* CFG_RAMBOOT */
147 #ifdef CONFIG_MGT5100
148 *(vu_long
*)MPC5XXX_ADDECR
|= (1 << 22); /* Enable SDRAM */
149 dramsize
= ((*(vu_long
*)MPC5XXX_SDRAM_STOP
+ 1) << 15);
151 dramsize
= ((1 << (*(vu_long
*)MPC5XXX_SDRAM_CS0CFG
- 0x13)) << 20);
152 #ifdef CONFIG_MPC5200_DDR
153 dramsize2
= ((1 << (*(vu_long
*)MPC5XXX_SDRAM_CS1CFG
- 0x13)) << 20);
156 #endif /* CFG_RAMBOOT */
158 #ifdef CONFIG_MPC5200_DDR
159 dramsize
+= dramsize2
;
161 /* return total ram size */
165 int checkboard (void)
167 #if defined(CONFIG_MPC5200)
168 puts ("Board: Motorola MPC5200 (IceCube)\n");
169 #elif defined(CONFIG_MGT5100)
170 puts ("Board: Motorola MGT5100 (IceCube)\n");
175 void flash_preinit(void)
178 * Now, when we are in RAM, enable flash write
179 * access for detection process.
180 * Note that CS_BOOT cannot be cleared when
181 * executing in flash.
183 #if defined(CONFIG_MGT5100)
184 *(vu_long
*)MPC5XXX_ADDECR
&= ~(1 << 25); /* disable CS_BOOT */
185 *(vu_long
*)MPC5XXX_ADDECR
|= (1 << 16); /* enable CS0 */
187 *(vu_long
*)MPC5XXX_BOOTCS_CFG
&= ~0x1; /* clear RO */
190 void flash_afterinit(ulong size
)
192 if (size
== 0x800000) { /* adjust mapping */
193 *(vu_long
*)MPC5XXX_BOOTCS_START
= *(vu_long
*)MPC5XXX_CS0_START
=
194 START_REG(CFG_BOOTCS_START
| size
);
195 *(vu_long
*)MPC5XXX_BOOTCS_STOP
= *(vu_long
*)MPC5XXX_CS0_STOP
=
196 STOP_REG(CFG_BOOTCS_START
| size
, size
);
201 static struct pci_controller hose
;
203 extern void pci_mpc5xxx_init(struct pci_controller
*);
205 void pci_init_board(void)
207 pci_mpc5xxx_init(&hose
);
211 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
213 #define GPIO_PSC1_4 0x01000000ul
215 void init_ide_reset (void)
217 printf ("init_ide_reset\n");
219 /* Configure PSC1_4 as GPIO output for ATA reset */
220 *(vu_long
*) MPC5XXX_WU_GPIO_DATA
|= GPIO_PSC1_4
;
221 *(vu_long
*) MPC5XXX_WU_GPIO_ENABLE
|= GPIO_PSC1_4
;
222 *(vu_long
*) MPC5XXX_WU_GPIO_DIR
|= GPIO_PSC1_4
;
225 void ide_set_reset (int idereset
)
227 printf ("ide_reset(%d)\n", idereset
);
229 *(vu_long
*) MPC5XXX_WU_GPIO_DATA
&= ~GPIO_PSC1_4
;
231 *(vu_long
*) MPC5XXX_WU_GPIO_DATA
|= GPIO_PSC1_4
;
234 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */