board/icecube/icecube.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc5xxx.h>
  29 #include <pci.h>
  30 #include <asm/processor.h>
  31
  32 #if defined(CONFIG_LITE5200B)
  33 #include "mt46v32m16.h"
  34 #else
  35 # if defined(CONFIG_MPC5200_DDR)
  36 #  include "mt46v16m16-75.h"
  37 # else
  38 #include "mt48lc16m16a2-75.h"
  39 # endif
  40 #endif
  41 #ifndef CFG_RAMBOOT
  42 static void sdram_start (int hi_addr)
  43 {
  44         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  45
  46         /* unlock mode register */
  47         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  48         __asm__ volatile ("sync");
  49
  50         /* precharge all banks */
  51         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  52         __asm__ volatile ("sync");
  53
  54 #if SDRAM_DDR
  55         /* set mode register: extended mode */
  56         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  57         __asm__ volatile ("sync");
  58
  59         /* set mode register: reset DLL */
  60         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  61         __asm__ volatile ("sync");
  62 #endif
  63
  64         /* precharge all banks */
  65         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  66         __asm__ volatile ("sync");
  67
  68         /* auto refresh */
  69         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  70         __asm__ volatile ("sync");
  71
  72         /* set mode register */
  73         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  74         __asm__ volatile ("sync");
  75
  76         /* normal operation */
  77         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  78         __asm__ volatile ("sync");
  79 }
  80 #endif
  81
  82 /*
  83  * ATTENTION: Although partially referenced initdram does NOT make real use
  84  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
  85  *            is something else than 0x00000000.
  86  */
  87
  88 #if defined(CONFIG_MPC5200)
  89 long int initdram (int board_type)
  90 {
  91         ulong dramsize = 0;
  92         ulong dramsize2 = 0;
  93         uint svr, pvr;
  94
  95 #ifndef CFG_RAMBOOT
  96         ulong test1, test2;
  97
  98         /* setup SDRAM chip selects */
  99         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
 100         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
 101         __asm__ volatile ("sync");
 102
 103         /* setup config registers */
 104         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 105         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 106         __asm__ volatile ("sync");
 107
 108 #if SDRAM_DDR
 109         /* set tap delay */
 110         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 111         __asm__ volatile ("sync");
 112 #endif
 113
 114         /* find RAM size using SDRAM CS0 only */
 115         sdram_start(0);
 116         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 117         sdram_start(1);
 118         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 119         if (test1 > test2) {
 120                 sdram_start(0);
 121                 dramsize = test1;
 122         } else {
 123                 dramsize = test2;
 124         }
 125
 126         /* memory smaller than 1MB is impossible */
 127         if (dramsize < (1 << 20)) {
 128                 dramsize = 0;
 129         }
 130
 131         /* set SDRAM CS0 size according to the amount of RAM found */
 132         if (dramsize > 0) {
 133                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 134         } else {
 135                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 136         }
 137
 138         /* let SDRAM CS1 start right after CS0 */
 139         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 140
 141         /* find RAM size using SDRAM CS1 only */
 142         if (!dramsize)
 143                 sdram_start(0);
 144         test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 145         if (!dramsize) {
 146                 sdram_start(1);
 147                 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 148         }
 149         if (test1 > test2) {
 150                 sdram_start(0);
 151                 dramsize2 = test1;
 152         } else {
 153                 dramsize2 = test2;
 154         }
 155
 156         /* memory smaller than 1MB is impossible */
 157         if (dramsize2 < (1 << 20)) {
 158                 dramsize2 = 0;
 159         }
 160
 161         /* set SDRAM CS1 size according to the amount of RAM found */
 162         if (dramsize2 > 0) {
 163                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 164                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 165         } else {
 166                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 167         }
 168
 169 #else /* CFG_RAMBOOT */
 170
 171         /* retrieve size of memory connected to SDRAM CS0 */
 172         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 173         if (dramsize >= 0x13) {
 174                 dramsize = (1 << (dramsize - 0x13)) << 20;
 175         } else {
 176                 dramsize = 0;
 177         }
 178
 179         /* retrieve size of memory connected to SDRAM CS1 */
 180         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 181         if (dramsize2 >= 0x13) {
 182                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 183         } else {
 184                 dramsize2 = 0;
 185         }
 186
 187 #endif /* CFG_RAMBOOT */
 188
 189         /*
 190          * On MPC5200B we need to set the special configuration delay in the
 191          * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 192          * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 193          *
 194          * "The SDelay should be written to a value of 0x00000004. It is
 195          * required to account for changes caused by normal wafer processing
 196          * parameters."
 197          */
 198         svr = get_svr();
 199         pvr = get_pvr();
 200         if ((SVR_MJREV(svr) >= 2) &&
 201             (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
 202
 203                 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
 204                 __asm__ volatile ("sync");
 205         }
 206
 207         return dramsize + dramsize2;
 208 }
 209
 210 #elif defined(CONFIG_MGT5100)
 211
 212 long int initdram (int board_type)
 213 {
 214         ulong dramsize = 0;
 215 #ifndef CFG_RAMBOOT
 216         ulong test1, test2;
 217
 218         /* setup and enable SDRAM chip selects */
 219         *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
 220         *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
 221         *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
 222         __asm__ volatile ("sync");
 223
 224         /* setup config registers */
 225         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 226         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 227
 228         /* address select register */
 229         *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
 230         __asm__ volatile ("sync");
 231
 232         /* find RAM size */
 233         sdram_start(0);
 234         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 235         sdram_start(1);
 236         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 237         if (test1 > test2) {
 238                 sdram_start(0);
 239                 dramsize = test1;
 240         } else {
 241                 dramsize = test2;
 242         }
 243
 244         /* set SDRAM end address according to size */
 245         *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 246
 247 #else /* CFG_RAMBOOT */
 248
 249         /* Retrieve amount of SDRAM available */
 250         dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 251
 252 #endif /* CFG_RAMBOOT */
 253
 254         return dramsize;
 255 }
 256
 257 #else
 258 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
 259 #endif
 260
 261 int checkboard (void)
 262 {
 263 #if defined (CONFIG_LITE5200B)
 264         puts ("Board: Freescale Lite5200B\n");
 265 #elif defined(CONFIG_MPC5200)
 266         puts ("Board: Motorola MPC5200 (IceCube)\n");
 267 #elif defined(CONFIG_MGT5100)
 268         puts ("Board: Motorola MGT5100 (IceCube)\n");
 269 #endif
 270         return 0;
 271 }
 272
 273 void flash_preinit(void)
 274 {
 275         /*
 276          * Now, when we are in RAM, enable flash write
 277          * access for detection process.
 278          * Note that CS_BOOT cannot be cleared when
 279          * executing in flash.
 280          */
 281 #if defined(CONFIG_MGT5100)
 282         *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
 283         *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
 284 #endif
 285         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 286 }
 287
 288 void flash_afterinit(ulong size)
 289 {
 290         if (size == 0x800000) { /* adjust mapping */
 291                 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 292                         START_REG(CFG_BOOTCS_START | size);
 293                 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 294                         STOP_REG(CFG_BOOTCS_START | size, size);
 295         }
 296 }
 297
 298 #ifdef  CONFIG_PCI
 299 static struct pci_controller hose;
 300
 301 extern void pci_mpc5xxx_init(struct pci_controller *);
 302
 303 void pci_init_board(void)
 304 {
 305         pci_mpc5xxx_init(&hose);
 306 }
 307 #endif
 308
 309 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
 310
 311 void init_ide_reset (void)
 312 {
 313         debug ("init_ide_reset\n");
 314
 315         /* Configure PSC1_4 as GPIO output for ATA reset */
 316         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 317         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 318         /* Deassert reset */
 319         *(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
 320 }
 321
 322 void ide_set_reset (int idereset)
 323 {
 324         debug ("ide_reset(%d)\n", idereset);
 325
 326         if (idereset) {
 327                 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
 328                 /* Make a delay. MPC5200 spec says 25 usec min */
 329                 udelay(500000);
 330         } else {
 331                 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
 332         }
 333 }
 334 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */