board/icecube/icecube.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <mpc5xxx.h>
  29 #include <pci.h>
  30 #include <asm/processor.h>
  31
  32 #if defined(CONFIG_OF_FLAT_TREE)
  33 #include <ft_build.h>
  34 #endif
  35
  36 #if defined(CONFIG_LITE5200B)
  37 #include "mt46v32m16.h"
  38 #else
  39 # if defined(CONFIG_MPC5200_DDR)
  40 #  include "mt46v16m16-75.h"
  41 # else
  42 #include "mt48lc16m16a2-75.h"
  43 # endif
  44 #endif
  45
  46 #ifdef CONFIG_LITE5200B_PM
  47 /* u-boot part of low-power mode implementation */
  48 #define SAVED_ADDR (*(void **)0x00000000)
  49 #define PSC2_4 0x02
  50
  51 void lite5200b_wakeup(void)
  52 {
  53         unsigned char wakeup_pin;
  54         void (*linux_wakeup)(void);
  55
  56         /* check PSC2_4, if it's down "QT" is signaling we have a wakeup
  57          * from low power mode */
  58         *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
  59         __asm__ volatile ("sync");
  60
  61         wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
  62         if (wakeup_pin & PSC2_4)
  63                 return;
  64
  65         /* acknowledge to "QT"
  66          * by holding pin at 1 for 10 uS */
  67         *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
  68         __asm__ volatile ("sync");
  69         *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
  70         __asm__ volatile ("sync");
  71         udelay(10);
  72
  73         /* put ram out of self-refresh */
  74         *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000;   /* mode_en */
  75         __asm__ volatile ("sync");
  76         *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000;   /* cke ref_en */
  77         __asm__ volatile ("sync");
  78         *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000;  /* !mode_en */
  79         __asm__ volatile ("sync");
  80         udelay(10); /* wait a bit */
  81
  82         /* jump back to linux kernel code */
  83         linux_wakeup = SAVED_ADDR;
  84         printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
  85                         linux_wakeup);
  86         linux_wakeup();
  87 }
  88 #else
  89 #define lite5200b_wakeup()
  90 #endif
  91
  92 #ifndef CFG_RAMBOOT
  93 static void sdram_start (int hi_addr)
  94 {
  95         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  96
  97         /* unlock mode register */
  98         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  99         __asm__ volatile ("sync");
 100
 101         /* precharge all banks */
 102         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
 103         __asm__ volatile ("sync");
 104
 105 #if SDRAM_DDR
 106         /* set mode register: extended mode */
 107         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
 108         __asm__ volatile ("sync");
 109
 110         /* set mode register: reset DLL */
 111         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
 112         __asm__ volatile ("sync");
 113 #endif
 114
 115         /* precharge all banks */
 116         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
 117         __asm__ volatile ("sync");
 118
 119         /* auto refresh */
 120         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
 121         __asm__ volatile ("sync");
 122
 123         /* set mode register */
 124         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
 125         __asm__ volatile ("sync");
 126
 127         /* normal operation */
 128         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
 129         __asm__ volatile ("sync");
 130 }
 131 #endif
 132
 133 /*
 134  * ATTENTION: Although partially referenced initdram does NOT make real use
 135  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
 136  *            is something else than 0x00000000.
 137  */
 138
 139 #if defined(CONFIG_MPC5200)
 140 long int initdram (int board_type)
 141 {
 142         ulong dramsize = 0;
 143         ulong dramsize2 = 0;
 144         uint svr, pvr;
 145
 146 #ifndef CFG_RAMBOOT
 147         ulong test1, test2;
 148
 149         /* setup SDRAM chip selects */
 150         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
 151         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
 152         __asm__ volatile ("sync");
 153
 154         /* setup config registers */
 155         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 156         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 157         __asm__ volatile ("sync");
 158
 159 #if SDRAM_DDR
 160         /* set tap delay */
 161         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 162         __asm__ volatile ("sync");
 163 #endif
 164
 165         /* find RAM size using SDRAM CS0 only */
 166         sdram_start(0);
 167         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 168         sdram_start(1);
 169         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 170         if (test1 > test2) {
 171                 sdram_start(0);
 172                 dramsize = test1;
 173         } else {
 174                 dramsize = test2;
 175         }
 176
 177         /* memory smaller than 1MB is impossible */
 178         if (dramsize < (1 << 20)) {
 179                 dramsize = 0;
 180         }
 181
 182         /* set SDRAM CS0 size according to the amount of RAM found */
 183         if (dramsize > 0) {
 184                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 185         } else {
 186                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 187         }
 188
 189         /* let SDRAM CS1 start right after CS0 */
 190         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 191
 192         /* find RAM size using SDRAM CS1 only */
 193         if (!dramsize)
 194                 sdram_start(0);
 195         test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 196         if (!dramsize) {
 197                 sdram_start(1);
 198                 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
 199         }
 200         if (test1 > test2) {
 201                 sdram_start(0);
 202                 dramsize2 = test1;
 203         } else {
 204                 dramsize2 = test2;
 205         }
 206
 207         /* memory smaller than 1MB is impossible */
 208         if (dramsize2 < (1 << 20)) {
 209                 dramsize2 = 0;
 210         }
 211
 212         /* set SDRAM CS1 size according to the amount of RAM found */
 213         if (dramsize2 > 0) {
 214                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 215                         | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 216         } else {
 217                 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 218         }
 219
 220 #else /* CFG_RAMBOOT */
 221
 222         /* retrieve size of memory connected to SDRAM CS0 */
 223         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 224         if (dramsize >= 0x13) {
 225                 dramsize = (1 << (dramsize - 0x13)) << 20;
 226         } else {
 227                 dramsize = 0;
 228         }
 229
 230         /* retrieve size of memory connected to SDRAM CS1 */
 231         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 232         if (dramsize2 >= 0x13) {
 233                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 234         } else {
 235                 dramsize2 = 0;
 236         }
 237
 238 #endif /* CFG_RAMBOOT */
 239
 240         /*
 241          * On MPC5200B we need to set the special configuration delay in the
 242          * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 243          * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 244          *
 245          * "The SDelay should be written to a value of 0x00000004. It is
 246          * required to account for changes caused by normal wafer processing
 247          * parameters."
 248          */
 249         svr = get_svr();
 250         pvr = get_pvr();
 251         if ((SVR_MJREV(svr) >= 2) &&
 252             (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
 253
 254                 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
 255                 __asm__ volatile ("sync");
 256         }
 257
 258         lite5200b_wakeup();
 259
 260         return dramsize + dramsize2;
 261 }
 262
 263 #elif defined(CONFIG_MGT5100)
 264
 265 long int initdram (int board_type)
 266 {
 267         ulong dramsize = 0;
 268 #ifndef CFG_RAMBOOT
 269         ulong test1, test2;
 270
 271         /* setup and enable SDRAM chip selects */
 272         *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
 273         *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
 274         *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
 275         __asm__ volatile ("sync");
 276
 277         /* setup config registers */
 278         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 279         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 280
 281         /* address select register */
 282         *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
 283         __asm__ volatile ("sync");
 284
 285         /* find RAM size */
 286         sdram_start(0);
 287         test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 288         sdram_start(1);
 289         test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
 290         if (test1 > test2) {
 291                 sdram_start(0);
 292                 dramsize = test1;
 293         } else {
 294                 dramsize = test2;
 295         }
 296
 297         /* set SDRAM end address according to size */
 298         *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 299
 300 #else /* CFG_RAMBOOT */
 301
 302         /* Retrieve amount of SDRAM available */
 303         dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 304
 305 #endif /* CFG_RAMBOOT */
 306
 307         return dramsize;
 308 }
 309
 310 #else
 311 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
 312 #endif
 313
 314 int checkboard (void)
 315 {
 316 #if defined (CONFIG_LITE5200B)
 317         puts ("Board: Freescale Lite5200B\n");
 318 #elif defined(CONFIG_MPC5200)
 319         puts ("Board: Motorola MPC5200 (IceCube)\n");
 320 #elif defined(CONFIG_MGT5100)
 321         puts ("Board: Motorola MGT5100 (IceCube)\n");
 322 #endif
 323         return 0;
 324 }
 325
 326 void flash_preinit(void)
 327 {
 328         /*
 329          * Now, when we are in RAM, enable flash write
 330          * access for detection process.
 331          * Note that CS_BOOT cannot be cleared when
 332          * executing in flash.
 333          */
 334 #if defined(CONFIG_MGT5100)
 335         *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
 336         *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
 337 #endif
 338         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 339 }
 340
 341 void flash_afterinit(ulong size)
 342 {
 343         if (size == 0x800000) { /* adjust mapping */
 344                 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 345                         START_REG(CFG_BOOTCS_START | size);
 346                 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 347                         STOP_REG(CFG_BOOTCS_START | size, size);
 348         }
 349 }
 350
 351 #ifdef  CONFIG_PCI
 352 static struct pci_controller hose;
 353
 354 extern void pci_mpc5xxx_init(struct pci_controller *);
 355
 356 void pci_init_board(void)
 357 {
 358         pci_mpc5xxx_init(&hose);
 359 }
 360 #endif
 361
 362 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 363
 364 void init_ide_reset (void)
 365 {
 366         debug ("init_ide_reset\n");
 367
 368         /* Configure PSC1_4 as GPIO output for ATA reset */
 369         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 370         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 371         /* Deassert reset */
 372         *(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
 373 }
 374
 375 void ide_set_reset (int idereset)
 376 {
 377         debug ("ide_reset(%d)\n", idereset);
 378
 379         if (idereset) {
 380                 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
 381                 /* Make a delay. MPC5200 spec says 25 usec min */
 382                 udelay(500000);
 383         } else {
 384                 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
 385         }
 386 }
 387 #endif
 388
 389 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 390 void
 391 ft_board_setup(void *blob, bd_t *bd)
 392 {
 393         ft_cpu_setup(blob, bd);
 394 }
 395 #endif