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git.ipfire.org Git - people/ms/u-boot.git/blob - board/icecube/icecube.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
32 #if defined(CONFIG_LITE5200B)
33 #include "mt46v32m16.h"
35 # if defined(CONFIG_MPC5200_DDR)
36 # include "mt46v16m16-75.h"
38 #include "mt48lc16m16a2-75.h"
42 static void sdram_start (int hi_addr
)
44 long hi_addr_bit
= hi_addr
? 0x01000000 : 0;
46 /* unlock mode register */
47 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000000 | hi_addr_bit
;
48 __asm__
volatile ("sync");
50 /* precharge all banks */
51 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
;
52 __asm__
volatile ("sync");
55 /* set mode register: extended mode */
56 *(vu_long
*)MPC5XXX_SDRAM_MODE
= SDRAM_EMODE
;
57 __asm__
volatile ("sync");
59 /* set mode register: reset DLL */
60 *(vu_long
*)MPC5XXX_SDRAM_MODE
= SDRAM_MODE
| 0x04000000;
61 __asm__
volatile ("sync");
64 /* precharge all banks */
65 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
;
66 __asm__
volatile ("sync");
69 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000004 | hi_addr_bit
;
70 __asm__
volatile ("sync");
72 /* set mode register */
73 *(vu_long
*)MPC5XXX_SDRAM_MODE
= SDRAM_MODE
;
74 __asm__
volatile ("sync");
76 /* normal operation */
77 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| hi_addr_bit
;
78 __asm__
volatile ("sync");
83 * ATTENTION: Although partially referenced initdram does NOT make real use
84 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
85 * is something else than 0x00000000.
88 #if defined(CONFIG_MPC5200)
89 long int initdram (int board_type
)
98 /* setup SDRAM chip selects */
99 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0x0000001e;/* 2G at 0x0 */
100 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= 0x80000000;/* disabled */
101 __asm__
volatile ("sync");
103 /* setup config registers */
104 *(vu_long
*)MPC5XXX_SDRAM_CONFIG1
= SDRAM_CONFIG1
;
105 *(vu_long
*)MPC5XXX_SDRAM_CONFIG2
= SDRAM_CONFIG2
;
106 __asm__
volatile ("sync");
110 *(vu_long
*)MPC5XXX_CDM_PORCFG
= SDRAM_TAPDELAY
;
111 __asm__
volatile ("sync");
114 /* find RAM size using SDRAM CS0 only */
116 test1
= get_ram_size((long *)CFG_SDRAM_BASE
, 0x80000000);
118 test2
= get_ram_size((long *)CFG_SDRAM_BASE
, 0x80000000);
126 /* memory smaller than 1MB is impossible */
127 if (dramsize
< (1 << 20)) {
131 /* set SDRAM CS0 size according to the amount of RAM found */
133 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0x13 + __builtin_ffs(dramsize
>> 20) - 1;
135 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0; /* disabled */
138 /* let SDRAM CS1 start right after CS0 */
139 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
+ 0x0000001e;/* 2G */
141 /* find RAM size using SDRAM CS1 only */
144 test2
= test1
= get_ram_size((long *)(CFG_SDRAM_BASE
+ dramsize
), 0x80000000);
147 test2
= get_ram_size((long *)(CFG_SDRAM_BASE
+ dramsize
), 0x80000000);
156 /* memory smaller than 1MB is impossible */
157 if (dramsize2
< (1 << 20)) {
161 /* set SDRAM CS1 size according to the amount of RAM found */
163 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
164 | (0x13 + __builtin_ffs(dramsize2
>> 20) - 1);
166 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
; /* disabled */
169 #else /* CFG_RAMBOOT */
171 /* retrieve size of memory connected to SDRAM CS0 */
172 dramsize
= *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
& 0xFF;
173 if (dramsize
>= 0x13) {
174 dramsize
= (1 << (dramsize
- 0x13)) << 20;
179 /* retrieve size of memory connected to SDRAM CS1 */
180 dramsize2
= *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
& 0xFF;
181 if (dramsize2
>= 0x13) {
182 dramsize2
= (1 << (dramsize2
- 0x13)) << 20;
187 #endif /* CFG_RAMBOOT */
190 * On MPC5200B we need to set the special configuration delay in the
191 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
192 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
194 * "The SDelay should be written to a value of 0x00000004. It is
195 * required to account for changes caused by normal wafer processing
200 if ((SVR_MJREV(svr
) >= 2) &&
201 (PVR_MAJ(pvr
) == 1) && (PVR_MIN(pvr
) == 4)) {
203 *(vu_long
*)MPC5XXX_SDRAM_SDELAY
= 0x04;
204 __asm__
volatile ("sync");
207 return dramsize
+ dramsize2
;
210 #elif defined(CONFIG_MGT5100)
212 long int initdram (int board_type
)
218 /* setup and enable SDRAM chip selects */
219 *(vu_long
*)MPC5XXX_SDRAM_START
= 0x00000000;
220 *(vu_long
*)MPC5XXX_SDRAM_STOP
= 0x0000ffff;/* 2G */
221 *(vu_long
*)MPC5XXX_ADDECR
|= (1 << 22); /* Enable SDRAM */
222 __asm__
volatile ("sync");
224 /* setup config registers */
225 *(vu_long
*)MPC5XXX_SDRAM_CONFIG1
= SDRAM_CONFIG1
;
226 *(vu_long
*)MPC5XXX_SDRAM_CONFIG2
= SDRAM_CONFIG2
;
228 /* address select register */
229 *(vu_long
*)MPC5XXX_SDRAM_XLBSEL
= SDRAM_ADDRSEL
;
230 __asm__
volatile ("sync");
234 test1
= get_ram_size((long *)CFG_SDRAM_BASE
, 0x80000000);
236 test2
= get_ram_size((long *)CFG_SDRAM_BASE
, 0x80000000);
244 /* set SDRAM end address according to size */
245 *(vu_long
*)MPC5XXX_SDRAM_STOP
= ((dramsize
- 1) >> 15);
247 #else /* CFG_RAMBOOT */
249 /* Retrieve amount of SDRAM available */
250 dramsize
= ((*(vu_long
*)MPC5XXX_SDRAM_STOP
+ 1) << 15);
252 #endif /* CFG_RAMBOOT */
258 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
261 int checkboard (void)
263 #if defined (CONFIG_LITE5200B)
264 puts ("Board: Freescale Lite5200B\n");
265 #elif defined(CONFIG_MPC5200)
266 puts ("Board: Motorola MPC5200 (IceCube)\n");
267 #elif defined(CONFIG_MGT5100)
268 puts ("Board: Motorola MGT5100 (IceCube)\n");
273 void flash_preinit(void)
276 * Now, when we are in RAM, enable flash write
277 * access for detection process.
278 * Note that CS_BOOT cannot be cleared when
279 * executing in flash.
281 #if defined(CONFIG_MGT5100)
282 *(vu_long
*)MPC5XXX_ADDECR
&= ~(1 << 25); /* disable CS_BOOT */
283 *(vu_long
*)MPC5XXX_ADDECR
|= (1 << 16); /* enable CS0 */
285 *(vu_long
*)MPC5XXX_BOOTCS_CFG
&= ~0x1; /* clear RO */
288 void flash_afterinit(ulong size
)
290 if (size
== 0x800000) { /* adjust mapping */
291 *(vu_long
*)MPC5XXX_BOOTCS_START
= *(vu_long
*)MPC5XXX_CS0_START
=
292 START_REG(CFG_BOOTCS_START
| size
);
293 *(vu_long
*)MPC5XXX_BOOTCS_STOP
= *(vu_long
*)MPC5XXX_CS0_STOP
=
294 STOP_REG(CFG_BOOTCS_START
| size
, size
);
299 static struct pci_controller hose
;
301 extern void pci_mpc5xxx_init(struct pci_controller
*);
303 void pci_init_board(void)
305 pci_mpc5xxx_init(&hose
);
309 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
311 void init_ide_reset (void)
313 debug ("init_ide_reset\n");
315 /* Configure PSC1_4 as GPIO output for ATA reset */
316 *(vu_long
*) MPC5XXX_WU_GPIO_ENABLE
|= GPIO_PSC1_4
;
317 *(vu_long
*) MPC5XXX_WU_GPIO_DIR
|= GPIO_PSC1_4
;
319 *(vu_long
*) MPC5XXX_WU_GPIO_DATA_O
|= GPIO_PSC1_4
;
322 void ide_set_reset (int idereset
)
324 debug ("ide_reset(%d)\n", idereset
);
327 *(vu_long
*) MPC5XXX_WU_GPIO_DATA_O
&= ~GPIO_PSC1_4
;
328 /* Make a delay. MPC5200 spec says 25 usec min */
331 *(vu_long
*) MPC5XXX_WU_GPIO_DATA_O
|= GPIO_PSC1_4
;
334 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */