board/icpdas/lp8x4x/lp8x4x.c

   1 /*
   2  * ICP DAS LP-8x4x Support
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  * adapted from Voipac PXA270 Support by
   6  * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/arch/hardware.h>
  26 #include <asm/arch/regs-mmc.h>
  27 #include <asm/arch/pxa.h>
  28 #include <netdev.h>
  29 #include <serial.h>
  30 #include <asm/io.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 /*
  35  * Miscelaneous platform dependent initialisations
  36  */
  37 int board_init(void)
  38 {
  39         /* We have RAM, disable cache */
  40         dcache_disable();
  41         icache_disable();
  42
  43         /* memory and cpu-speed are setup before relocation */
  44         /* so we do _nothing_ here */
  45
  46         /* adress of boot parameters */
  47         gd->bd->bi_boot_params = 0xa0000100;
  48
  49         return 0;
  50 }
  51
  52 int dram_init(void)
  53 {
  54         pxa2xx_dram_init();
  55         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  56         return 0;
  57 }
  58
  59 void dram_init_banksize(void)
  60 {
  61         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  62         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  63 }
  64
  65 #ifdef  CONFIG_CMD_MMC
  66 int board_mmc_init(bd_t *bis)
  67 {
  68         pxa_mmc_register(0);
  69         return 0;
  70 }
  71 #endif
  72
  73 #ifdef  CONFIG_CMD_USB
  74 int usb_board_init(void)
  75 {
  76         writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
  77                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  78                 UHCHR);
  79
  80         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  81
  82         while (readl(UHCHR) & UHCHR_FSBIR)
  83                 continue; /* required by checkpath.pl */
  84
  85         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  86         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  87
  88         /* Clear any OTG Pin Hold */
  89         if (readl(PSSR) & PSSR_OTGPH)
  90                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  91
  92         writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  93         writel(readl(UHCRHDA) | 0x100, UHCRHDA);
  94
  95         /* Set port power control mask bits, only 3 ports. */
  96         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  97
  98         /* enable port 2 */
  99         writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
 100                 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
 101
 102         return 0;
 103 }
 104
 105 void usb_board_init_fail(void)
 106 {
 107         return;
 108 }
 109
 110 void usb_board_stop(void)
 111 {
 112         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 113         udelay(11);
 114         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 115
 116         writel(readl(UHCCOMS) | 1, UHCCOMS);
 117         udelay(10);
 118
 119         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 120
 121         return;
 122 }
 123 #endif
 124
 125 #ifdef CONFIG_DRIVER_DM9000
 126 void lp8x4x_eth1_mac_init(void)
 127 {
 128         u8 eth1addr[8];
 129         int i;
 130         u8 reg;
 131
 132         eth_getenv_enetaddr_by_index("eth", 1, eth1addr);
 133         if (!is_valid_ether_addr(eth1addr))
 134                 return;
 135
 136         for (i = 0, reg = 0x10; i < 6; i++, reg++) {
 137                 writeb(reg, (u8 *)(DM9000_IO_2));
 138                 writeb(eth1addr[i], (u8 *)(DM9000_DATA_2));
 139         }
 140 }
 141
 142 int board_eth_init(bd_t *bis)
 143 {
 144         lp8x4x_eth1_mac_init();
 145         return dm9000_initialize(bis);
 146 }
 147 #endif