]>
git.ipfire.org Git - people/ms/u-boot.git/blob - board/ids/ids8247/ids8247.c
3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
12 #if defined(CONFIG_OF_LIBFDT)
14 #include <libfdt_env.h>
15 #include <fdt_support.h>
18 DECLARE_GLOBAL_DATA_PTR
;
21 * I/O Port configuration table
23 * if conf is 1, then that port pin will be configured at boot time
24 * according to the five values podr/pdir/ppar/psor/pdat for that entry
27 const iop_conf_t iop_conf_tab
[4][32] = {
29 /* Port A configuration */
30 { /* conf ppar psor pdir podr pdat */
31 /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
32 /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
33 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
34 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
35 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
36 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
37 /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */
38 #if defined(CONFIG_SYS_I2C_SOFT)
39 /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */
40 /* PA23 */ { 1, 0, 0, 1, 1, 1 }, /* I2C_SCL2 */
41 #else /* normal I/O port pins */
42 /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
43 /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
45 /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */
46 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
47 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
48 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
49 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
50 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
51 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
52 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
53 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
54 /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */
55 /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */
56 /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */
57 /* PA10 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DSR */
58 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
59 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
60 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
61 /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
62 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
63 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
64 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
65 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
66 /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
67 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
70 /* Port B configuration */
71 { /* conf ppar psor pdir podr pdat */
72 /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
73 /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
74 /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
75 /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
76 /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
77 /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
78 /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
79 /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
80 /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
81 /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
82 /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
83 /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
84 /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
85 /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
86 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
87 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
88 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
89 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
90 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
91 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
92 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
93 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
94 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
95 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
96 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
97 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
98 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
99 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
100 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
101 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
102 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
103 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
107 { /* conf ppar psor pdir podr pdat */
108 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
109 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
110 /* PC29 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CLSN */
111 /* PC28 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_OUT */
112 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
113 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
114 /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */
115 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
116 /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
117 /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
118 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
119 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
120 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
121 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
122 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
123 /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
124 /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
125 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
126 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
127 /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
128 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
129 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
130 /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
131 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
132 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
133 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
134 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
135 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
136 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
137 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
138 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
139 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
143 { /* conf ppar psor pdir podr pdat */
144 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
145 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
146 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
147 /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
148 /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
149 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
150 /* PD25 */ { 0, 1, 0, 0, 0, 0 }, /* SCC3_RX */
151 /* PD24 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_TX */
152 /* PD23 */ { 0, 1, 0, 1, 0, 0 }, /* SCC3_RTS */
153 /* PD22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC4_RXD */
154 /* PD21 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_TXD */
155 /* PD20 */ { 0, 1, 0, 1, 0, 0 }, /* SCC4_RTS */
156 /* PD19 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_SEL */
157 /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_CLK */
158 /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MOSI */
159 /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPI_MISO */
160 #if defined(CONFIG_HARD_I2C)
161 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA1 */
162 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL1 */
163 #else /* normal I/O port pins */
164 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* PD15 */
165 /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* PD14 */
167 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
168 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
169 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
170 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
171 /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
172 /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
173 /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */
174 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
175 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
176 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
177 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
178 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
179 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
180 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
184 /* ------------------------------------------------------------------------- */
186 /* Check Board Identity:
188 int checkboard (void)
190 puts ("Board: IDS 8247\n");
194 /* ------------------------------------------------------------------------- */
196 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
198 * This routine performs standard 8260 initialization sequence
199 * and calculates the available memory size. It may be called
200 * several times to try different SDRAM configurations on both
201 * 60x and local buses.
203 static long int try_init (volatile memctl8260_t
* memctl
, ulong sdmr
,
204 ulong orx
, volatile uchar
* base
)
206 volatile uchar c
= 0xff;
207 volatile uint
*sdmr_ptr
;
208 volatile uint
*orx_ptr
;
212 /* We must be able to test a location outsize the maximum legal size
213 * to find out THAT we are outside; but this address still has to be
214 * mapped by the controller. That means, that the initial mapping has
215 * to be (at least) twice as large as the maximum expected size.
217 maxsize
= (1 + (~orx
| 0x7fff))/* / 2*/;
219 sdmr_ptr
= &memctl
->memc_psdmr
;
220 orx_ptr
= &memctl
->memc_or2
;
225 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
227 * "At system reset, initialization software must set up the
228 * programmable parameters in the memory controller banks registers
229 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
230 * system software should execute the following initialization sequence
231 * for each SDRAM device.
233 * 1. Issue a PRECHARGE-ALL-BANKS command
234 * 2. Issue eight CBR REFRESH commands
235 * 3. Issue a MODE-SET command to initialize the mode register
237 * The initial commands are executed by setting P/LSDMR[OP] and
238 * accessing the SDRAM with a single-byte transaction."
240 * The appropriate BRx/ORx registers have already been set when we
241 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
244 *sdmr_ptr
= sdmr
| PSDMR_OP_PREA
;
247 *sdmr_ptr
= sdmr
| PSDMR_OP_CBRR
;
248 for (i
= 0; i
< 8; i
++)
251 *sdmr_ptr
= sdmr
| PSDMR_OP_MRW
;
252 *(base
+ CONFIG_SYS_MRS_OFFS
) = c
; /* setting MR on address lines */
254 *sdmr_ptr
= sdmr
| PSDMR_OP_NORM
| PSDMR_RFEN
;
257 size
= get_ram_size((long *)base
, maxsize
);
258 *orx_ptr
= orx
| ~(size
- 1);
263 phys_size_t
initdram (int board_type
)
265 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
266 volatile memctl8260_t
*memctl
= &immap
->im_memctl
;
270 psize
= 16 * 1024 * 1024;
272 memctl
->memc_psrt
= CONFIG_SYS_PSRT
;
273 memctl
->memc_mptpr
= CONFIG_SYS_MPTPR
;
275 #ifndef CONFIG_SYS_RAMBOOT
278 psize
= try_init (memctl
, CONFIG_SYS_PSDMR
, CONFIG_SYS_OR2
,
279 (uchar
*) CONFIG_SYS_SDRAM_BASE
);
280 #endif /* CONFIG_SYS_RAMBOOT */
287 int misc_init_r (void)
289 gd
->bd
->bi_flashstart
= 0xff800000;
293 #if defined(CONFIG_CMD_NAND)
295 #include <linux/mtd/mtd.h>
300 static void ids_nand_hwctrl(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
302 struct nand_chip
*this = mtd
->priv
;
304 if (ctrl
& NAND_CTRL_CHANGE
) {
305 if ( ctrl
& NAND_CLE
) {
307 writeb(0x00, (this->IO_ADDR_W
+ 0x0a));
310 writeb(0x00, (this->IO_ADDR_W
+ 0x08));
312 if ( ctrl
& NAND_ALE
) {
314 writeb(0x00, (this->IO_ADDR_W
+ 0x09));
317 writeb(0x00, (this->IO_ADDR_W
+ 0x08));
319 if ( (ctrl
& NAND_NCE
) != NAND_NCE
)
320 writeb(0x00, (this->IO_ADDR_W
+ 0x0c));
322 writeb(0x00, (this->IO_ADDR_W
+ 0x08));
324 if (cmd
!= NAND_CMD_NONE
)
325 writeb(cmd
, this->IO_ADDR_W
);
329 static u_char
ids_nand_read_byte(struct mtd_info
*mtd
)
331 struct nand_chip
*this = mtd
->priv
;
333 return readb(this->IO_ADDR_R
);
336 static void ids_nand_write_buf(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
338 struct nand_chip
*nand
= mtd
->priv
;
341 for (i
= 0; i
< len
; i
++) {
343 writeb(buf
[i
], (nand
->IO_ADDR_W
+ 0x02));
344 else if (hwctl
& 0x2)
345 writeb(buf
[i
], (nand
->IO_ADDR_W
+ 0x01));
347 writeb(buf
[i
], nand
->IO_ADDR_W
);
351 static void ids_nand_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
353 struct nand_chip
*this = mtd
->priv
;
356 for (i
= 0; i
< len
; i
++) {
357 buf
[i
] = readb(this->IO_ADDR_R
);
361 static int ids_nand_dev_ready(struct mtd_info
*mtd
)
363 /* constant delay (see also tR in the datasheet) */
368 int board_nand_init(struct nand_chip
*nand
)
370 nand
->ecc
.mode
= NAND_ECC_SOFT
;
372 /* Reference hardware control function */
373 nand
->cmd_ctrl
= ids_nand_hwctrl
;
374 nand
->read_byte
= ids_nand_read_byte
;
375 nand
->write_buf
= ids_nand_write_buf
;
376 nand
->read_buf
= ids_nand_read_buf
;
377 nand
->dev_ready
= ids_nand_dev_ready
;
378 nand
->chip_delay
= 12;
383 #endif /* CONFIG_CMD_NAND */
385 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
386 void ft_board_setup(void *blob
, bd_t
*bd
)
388 ft_cpu_setup( blob
, bd
);
390 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */