2 * Partially derived from board code for digsyMTC,
4 * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
7 * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/processor.h>
17 #include <fdt_support.h>
23 DECLARE_GLOBAL_DATA_PTR
;
25 #define SDRAM_MODE 0x00CD0000
26 #define SDRAM_CONTROL 0x504F0000
27 #define SDRAM_CONFIG1 0xD2322800
28 #define SDRAM_CONFIG2 0x8AD70000
30 enum ifm_sensor_type
{
31 O2DNT
= 0x00, /* !< O2DNT 32MB */
32 O2DNT2
= 0x01, /* !< O2DNT2 64MB */
33 O3DNT
= 0x02, /* !< O3DNT 32MB */
34 O3DNT_MIN
= 0x40, /* !< O3DNT Minerva 32MB */
35 UNKNOWN
= 0xff, /* !< Unknow sensor */
38 static enum ifm_sensor_type gt_ifm_sensor_type
;
40 #ifndef CONFIG_SYS_RAMBOOT
41 static void sdram_start(int hi_addr
)
43 struct mpc5xxx_sdram
*sdram
= (struct mpc5xxx_sdram
*)MPC5XXX_SDRAM
;
44 long hi_addr_bit
= hi_addr
? 0x01000000 : 0;
45 long control
= SDRAM_CONTROL
| hi_addr_bit
;
47 /* unlock mode register */
48 out_be32(&sdram
->ctrl
, control
| 0x80000000);
50 /* precharge all banks */
51 out_be32(&sdram
->ctrl
, control
| 0x80000002);
54 out_be32(&sdram
->ctrl
, control
| 0x80000004);
56 /* set mode register */
57 out_be32(&sdram
->mode
, SDRAM_MODE
);
59 /* normal operation */
60 out_be32(&sdram
->ctrl
, control
);
65 * ATTENTION: Although partially referenced initdram does NOT make real use
66 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
67 * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
69 phys_size_t
initdram(void)
71 struct mpc5xxx_mmap_ctl
*mmap_ctl
=
72 (struct mpc5xxx_mmap_ctl
*)CONFIG_SYS_MBAR
;
73 struct mpc5xxx_sdram
*sdram
= (struct mpc5xxx_sdram
*)MPC5XXX_SDRAM
;
78 if (gt_ifm_sensor_type
== O2DNT2
) {
79 /* activate SDRAM CS1 */
80 setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG
, 0x80000000);
83 #ifndef CONFIG_SYS_RAMBOOT
86 /* setup SDRAM chip selects */
87 out_be32(&mmap_ctl
->sdram0
, 0x0000001E); /* 2 GB at 0x0 */
88 out_be32(&mmap_ctl
->sdram1
, 0x00000000); /* disabled */
90 /* setup config registers */
91 out_be32(&sdram
->config1
, SDRAM_CONFIG1
);
92 out_be32(&sdram
->config2
, SDRAM_CONFIG2
);
94 /* find RAM size using SDRAM CS0 only */
96 test1
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x08000000);
98 test2
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x08000000);
106 /* memory smaller than 1MB is impossible */
107 if (dramsize
< (1 << 20))
110 /* set SDRAM CS0 size according to the amount of RAM found */
112 out_be32(&mmap_ctl
->sdram0
,
113 (0x13 + __builtin_ffs(dramsize
>> 20) - 1));
115 out_be32(&mmap_ctl
->sdram0
, 0); /* disabled */
118 /* let SDRAM CS1 start right after CS0 */
119 out_be32(&mmap_ctl
->sdram1
, dramsize
+ 0x0000001E); /* 2G */
121 /* find RAM size using SDRAM CS1 only */
125 test2
= test1
= get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE
+ dramsize
),
129 test2
= get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE
+ dramsize
),
140 /* memory smaller than 1MB is impossible */
141 if (dramsize2
< (1 << 20))
144 /* set SDRAM CS1 size according to the amount of RAM found */
146 out_be32(&mmap_ctl
->sdram1
, (dramsize
|
147 (0x13 + __builtin_ffs(dramsize2
>> 20) - 1)));
149 out_be32(&mmap_ctl
->sdram1
, dramsize
); /* disabled */
152 #else /* CONFIG_SYS_RAMBOOT */
153 /* retrieve size of memory connected to SDRAM CS0 */
154 dramsize
= in_be32(&mmap_ctl
->sdram0
) & 0xFF;
155 if (dramsize
>= 0x13)
156 dramsize
= (1 << (dramsize
- 0x13)) << 20;
160 /* retrieve size of memory connected to SDRAM CS1 */
161 dramsize2
= in_be32(&mmap_ctl
->sdram1
) & 0xFF;
162 if (dramsize2
>= 0x13)
163 dramsize2
= (1 << (dramsize2
- 0x13)) << 20;
167 #endif /* CONFIG_SYS_RAMBOOT */
170 * On MPC5200B we need to set the special configuration delay in the
171 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
172 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
174 * "The SDelay should be written to a value of 0x00000004. It is
175 * required to account for changes caused by normal wafer processing
180 if ((SVR_MJREV(svr
) >= 2) &&
181 (PVR_MAJ(pvr
) == 1) && (PVR_MIN(pvr
) == 4))
182 out_be32(&sdram
->sdelay
, 0x04);
184 return dramsize
+ dramsize2
;
188 #define GPT_GPIO_IN 0x4
192 struct mpc5xxx_gpt
*gpt
= (struct mpc5xxx_gpt
*)MPC5XXX_GPT
;
193 unsigned char board_config
= 0;
196 /* switch gpt0 - gpt7 to input */
197 for (i
= 0; i
< 7; i
++)
198 out_be32(&gpt
[i
].emsr
, GPT_GPIO_IN
);
200 /* get configuration byte on timer-port */
201 for (i
= 0; i
< 7; i
++)
202 board_config
|= (in_be32(&gpt
[i
].sr
) & 0x100) >> (8 - i
);
206 switch (board_config
) {
209 gt_ifm_sensor_type
= O2DNT
;
213 gt_ifm_sensor_type
= O3DNT
;
217 gt_ifm_sensor_type
= O2DNT2
;
220 puts("O3DNT Minerva\n");
221 gt_ifm_sensor_type
= O3DNT_MIN
;
225 gt_ifm_sensor_type
= UNKNOWN
;
232 int board_early_init_r(void)
234 struct mpc5xxx_lpb
*lpb_regs
= (struct mpc5xxx_lpb
*)MPC5XXX_LPB
;
237 * Now, when we are in RAM, enable flash write access for detection
238 * process. Note that CS_BOOT cannot be cleared when executing in flash.
240 clrbits_be32(&lpb_regs
->cs0_cfg
, 1); /* clear RO */
241 /* disable CS_BOOT */
242 clrbits_be32((void *)MPC5XXX_ADDECR
, (1 << 25));
244 setbits_be32((void *)MPC5XXX_ADDECR
, (1 << 16));
249 #define MIIM_LXT971_LED_CFG_REG 0x14
250 #define LXT971_LED_CFG_LINK_STATUS 0x4000
251 #define LXT971_LED_CFG_RX_TX_ACTIVITY 0x0700
252 #define LXT971_LED_CFG_LINK_ACTIVITY 0x00D0
253 #define LXT971_LED_CFG_PULSE_STRETCH 0x0002
255 * Additional PHY intialization after reset in mpc5xxx_fec_init_phy()
260 * Set LED configuration bits.
261 * It can't be done in misc_init_r() since FEC is not
262 * initialized at this time. Therefore we do it here.
264 miiphy_write("FEC", CONFIG_PHY_ADDR
, MIIM_LXT971_LED_CFG_REG
,
265 LXT971_LED_CFG_LINK_STATUS
|
266 LXT971_LED_CFG_RX_TX_ACTIVITY
|
267 LXT971_LED_CFG_LINK_ACTIVITY
|
268 LXT971_LED_CFG_PULSE_STRETCH
);
271 #if defined(CONFIG_POST)
273 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
274 * is left open, no keypress is detected.
276 int post_hotkeys_pressed(void)
278 struct mpc5xxx_gpio
*gpio
= (struct mpc5xxx_gpio
*) MPC5XXX_GPIO
;
281 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
282 * CODEC or UART mode. Consumer IrDA should still be possible.
284 clrbits_be32(&gpio
->port_config
, 0x07000000);
285 setbits_be32(&gpio
->port_config
, 0x03000000);
287 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
288 setbits_be32(&gpio
->simple_gpioe
, 0x20000000);
290 /* Configure GPIO_IRDA_1 as input */
291 clrbits_be32(&gpio
->simple_ddr
, 0x20000000);
293 return (in_be32(&gpio
->simple_ival
) & 0x20000000) ? 0 : 1;
298 static struct pci_controller hose
;
300 void pci_init_board(void)
302 pci_mpc5xxx_init(&hose
);
306 #ifdef CONFIG_OF_BOARD_SETUP
307 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
308 static void ft_adapt_flash_base(void *blob
)
310 flash_info_t
*dev
= &flash_info
[0];
312 struct fdt_property
*prop
;
316 off
= fdt_node_offset_by_compatible(blob
, -1, "fsl,mpc5200b-lpb");
318 printf("Could not find fsl,mpc5200b-lpb node.\n");
322 /* found compatible property */
323 prop
= fdt_get_property_w(blob
, off
, "ranges", &len
);
325 reg
= reg2
= (u32
*)&prop
->data
[0];
327 reg
[2] = dev
->start
[0];
329 fdt_setprop(blob
, off
, "ranges", reg2
, len
);
331 printf("Could not find ranges\n");
334 extern ulong
flash_get_size(phys_addr_t base
, int banknum
);
336 /* Update the flash baseaddr settings */
337 int update_flash_size(int flash_size
)
339 struct mpc5xxx_mmap_ctl
*mm
=
340 (struct mpc5xxx_mmap_ctl
*) CONFIG_SYS_MBAR
;
344 unsigned long base
= 0x0;
345 u32
*cs_reg
= (u32
*)&mm
->cs0_start
;
347 for (i
= 0; i
< 2; i
++) {
348 dev
= &flash_info
[i
];
351 /* calculate new base addr for this chipselect */
353 out_be32(cs_reg
, START_REG(base
));
355 out_be32(cs_reg
, STOP_REG(base
, dev
->size
));
357 /* recalculate the sectoraddr in the cfi driver */
358 size
+= flash_get_size(base
, i
);
361 flash_protect_default();
362 gd
->bd
->bi_flashstart
= base
;
365 #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
367 int ft_board_setup(void *blob
, bd_t
*bd
)
369 int phy_addr
= CONFIG_PHY_ADDR
;
370 char eth_path
[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
372 ft_cpu_setup(blob
, bd
);
374 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
375 #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
376 /* Update reg property in all nor flash nodes too */
377 fdt_fixup_nor_flash_size(blob
);
379 ft_adapt_flash_base(blob
);
381 /* fix up the phy address */
382 do_fixup_by_path(blob
, eth_path
, "reg", &phy_addr
, sizeof(int), 0);
386 #endif /* CONFIG_OF_BOARD_SETUP */