1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (C) 2013 Imagination Technologies
12 #include <pci_gt64120.h>
13 #include <pci_msc01.h>
16 #include <asm/addrspace.h>
18 #include <asm/malta.h>
22 DECLARE_GLOBAL_DATA_PTR
;
36 static void malta_lcd_puts(const char *str
)
39 void *reg
= (void *)CKSEG1ADDR(MALTA_ASCIIPOS0
);
41 /* print up to 8 characters of the string */
42 for (i
= 0; i
< min((int)strlen(str
), 8); i
++) {
43 __raw_writel(str
[i
], reg
);
44 reg
+= MALTA_ASCIIPOS1
- MALTA_ASCIIPOS0
;
47 /* fill the rest of the display with spaces */
49 __raw_writel(' ', reg
);
50 reg
+= MALTA_ASCIIPOS1
- MALTA_ASCIIPOS0
;
54 static enum core_card
malta_core_card(void)
57 const void *reg
= (const void *)CKSEG1ADDR(MALTA_REVISION
);
59 rev
= __raw_readl(reg
);
60 corid
= (rev
& MALTA_REVISION_CORID_MSK
) >> MALTA_REVISION_CORID_SHF
;
63 case MALTA_REVISION_CORID_CORE_LV
:
66 case MALTA_REVISION_CORID_CORE_FPGA6
:
74 static enum sys_con
malta_sys_con(void)
76 switch (malta_core_card()) {
78 return SYSCON_GT64120
;
84 return SYSCON_UNKNOWN
;
90 gd
->ram_size
= CONFIG_SYS_MEM_SIZE
;
99 malta_lcd_puts("U-Boot");
100 puts("Board: MIPS Malta");
102 core
= malta_core_card();
113 puts(" CoreUnknown");
120 int board_eth_init(bd_t
*bis
)
122 return pci_eth_init(bis
);
125 void _machine_restart(void)
127 void __iomem
*reset_base
;
129 reset_base
= (void __iomem
*)CKSEG1ADDR(MALTA_RESET_BASE
);
130 __raw_writel(GORESET
, reset_base
);
134 int board_early_init_f(void)
138 /* choose correct PCI I/O base */
139 switch (malta_sys_con()) {
141 io_base
= CKSEG1ADDR(MALTA_GT_PCIIO_BASE
);
145 io_base
= CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE
);
152 set_io_port_base(io_base
);
154 /* setup FDC37M817 super I/O controller */
155 malta_superio_init();
160 int misc_init_r(void)
167 void pci_init_board(void)
173 switch (malta_sys_con()) {
175 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE
),
176 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE
,
177 0x10000000, 0x10000000, 128 * 1024 * 1024,
178 0x00000000, 0x00000000, 0x20000);
183 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE
),
184 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE
,
185 MALTA_MSC01_PCIMEM_MAP
,
186 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE
),
187 MALTA_MSC01_PCIMEM_SIZE
, MALTA_MSC01_PCIIO_MAP
,
188 0x00000000, MALTA_MSC01_PCIIO_SIZE
);
192 bdf
= pci_find_device(PCI_VENDOR_ID_INTEL
,
193 PCI_DEVICE_ID_INTEL_82371AB_0
, 0);
195 panic("Failed to find PIIX4 PCI bridge\n");
197 /* setup PCI interrupt routing */
198 pci_write_config_byte(bdf
, PCI_CFG_PIIX4_PIRQRCA
, 10);
199 pci_write_config_byte(bdf
, PCI_CFG_PIIX4_PIRQRCB
, 10);
200 pci_write_config_byte(bdf
, PCI_CFG_PIIX4_PIRQRCC
, 11);
201 pci_write_config_byte(bdf
, PCI_CFG_PIIX4_PIRQRCD
, 11);
203 /* mux SERIRQ onto SERIRQ pin */
204 pci_read_config_dword(bdf
, PCI_CFG_PIIX4_GENCFG
, &val32
);
205 val32
|= PCI_CFG_PIIX4_GENCFG_SERIRQ
;
206 pci_write_config_dword(bdf
, PCI_CFG_PIIX4_GENCFG
, val32
);
208 /* enable SERIRQ - Linux currently depends upon this */
209 pci_read_config_byte(bdf
, PCI_CFG_PIIX4_SERIRQC
, &val8
);
210 val8
|= PCI_CFG_PIIX4_SERIRQC_EN
| PCI_CFG_PIIX4_SERIRQC_CONT
;
211 pci_write_config_byte(bdf
, PCI_CFG_PIIX4_SERIRQC
, val8
);
213 bdf
= pci_find_device(PCI_VENDOR_ID_INTEL
,
214 PCI_DEVICE_ID_INTEL_82371AB
, 0);
216 panic("Failed to find PIIX4 IDE controller\n");
218 /* enable bus master & IO access */
219 val32
|= PCI_COMMAND_MASTER
| PCI_COMMAND_IO
;
220 pci_write_config_dword(bdf
, PCI_COMMAND
, val32
);
223 pci_write_config_byte(bdf
, PCI_LATENCY_TIMER
, 0x40);
226 pci_write_config_dword(bdf
, PCI_CFG_PIIX4_IDETIM_PRI
,
227 PCI_CFG_PIIX4_IDETIM_IDE
);
228 pci_write_config_dword(bdf
, PCI_CFG_PIIX4_IDETIM_SEC
,
229 PCI_CFG_PIIX4_IDETIM_IDE
);