3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/sys_proto.h>
16 DECLARE_GLOBAL_DATA_PTR
;
20 /* dram_init must store complete ramsize in gd->ram_size */
21 gd
->ram_size
= get_ram_size((void *)PHYS_SDRAM_1
,
29 gd
->bd
->bi_arch_number
= MACH_TYPE_PCM037
; /* board id for linux */
30 gd
->bd
->bi_boot_params
= (0x80000100); /* adress of boot parameters */
35 int board_early_init_f(void)
38 static const struct mxc_weimcs cs0
= {
39 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
40 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
41 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
42 CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
43 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
44 CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
47 /* CS1: Network Controller */
48 static const struct mxc_weimcs cs1
= {
49 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
50 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6),
51 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
52 CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
53 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
54 CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
58 static const struct mxc_weimcs cs4
= {
59 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
60 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
61 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
62 CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
63 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
64 CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
67 mxc_setup_weimcs(0, &cs0
);
68 mxc_setup_weimcs(1, &cs1
);
69 mxc_setup_weimcs(4, &cs4
);
71 /* setup pins for UART1 */
72 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX
);
73 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX
);
74 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B
);
75 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B
);
77 /* setup pins for I2C2 (for EEPROM, RTC) */
78 mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL
);
79 mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA
);
84 #ifdef CONFIG_BOARD_LATE_INIT
85 int board_late_init(void)
88 struct s6e63d6 data
= {
90 * See comment in mxc_spi.c::decode_cs() for .cs field format.
91 * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
92 * 2 of the SPI controller #1, since it is unused.
101 mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK
);
102 mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B
);
103 mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI
);
104 mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO
);
105 mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B
);
106 mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B
);
107 mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B
);
109 /* start SPI1 clock */
110 __REG(CCM_CGR2
) = __REG(CCM_CGR2
) | (3 << 2);
113 /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
114 mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO
));
116 /* SPI1 CS2 is free */
117 ret
= s6e63d6_init(&data
);
122 * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
123 * OLED display connected to a S6E63D6 SPI display controller in the
126 s6e63d6_index(&data
, 2);
127 s6e63d6_param(&data
, 0x0182);
128 s6e63d6_index(&data
, 3);
129 s6e63d6_param(&data
, 0x8130);
130 s6e63d6_index(&data
, 0x10);
131 s6e63d6_param(&data
, 0x0000);
132 s6e63d6_index(&data
, 5);
133 s6e63d6_param(&data
, 0x0001);
134 s6e63d6_index(&data
, 0x22);
140 int checkboard (void)
142 printf("Board: Phytec phyCore i.MX31\n");
146 int board_eth_init(bd_t
*bis
)
149 #ifdef CONFIG_SMC911X
150 rc
= smc911x_initialize(0, CONFIG_SMC911X_BASE
);