board/imx31_phycore/imx31_phycore.c

   1 /*
   2  *
   3  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24
  25 #include <common.h>
  26 #include <s6e63d6.h>
  27 #include <netdev.h>
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/imx-regs.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 int dram_init(void)
  34 {
  35         /* dram_init must store complete ramsize in gd->ram_size */
  36         gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
  37                                 PHYS_SDRAM_1_SIZE);
  38         return 0;
  39 }
  40
  41 int board_init(void)
  42 {
  43
  44         gd->bd->bi_arch_number = MACH_TYPE_PCM037;      /* board id for linux */
  45         gd->bd->bi_boot_params = (0x80000100);  /* adress of boot parameters */
  46
  47         return 0;
  48 }
  49
  50 int board_early_init_f(void)
  51 {
  52         __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
  53         __REG(CSCR_L(0)) = 0x10000d03;
  54         __REG(CSCR_A(0)) = 0x00720900;
  55
  56         __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
  57         __REG(CSCR_L(1)) = 0x444a4541;
  58         __REG(CSCR_A(1)) = 0x44443302;
  59
  60         __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
  61         __REG(CSCR_L(4)) = 0x22252521;
  62         __REG(CSCR_A(4)) = 0x22220a00;
  63
  64         /* setup pins for UART1 */
  65         mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
  66         mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
  67         mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
  68         mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
  69
  70         /* setup pins for I2C2 (for EEPROM, RTC) */
  71         mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
  72         mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
  73
  74         return 0;
  75 }
  76
  77 #ifdef BOARD_LATE_INIT
  78 int board_late_init(void)
  79 {
  80 #ifdef CONFIG_S6E63D6
  81         struct s6e63d6 data = {
  82                 /*
  83                  * See comment in mxc_spi.c::decode_cs() for .cs field format.
  84                  * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
  85                  * 2 of the SPI controller #1, since it is unused.
  86                  */
  87                 .cs = 2 | (57 << 8),
  88                 .bus = 0,
  89                 .id = 0,
  90         };
  91         int ret;
  92
  93         /* SPI1 */
  94         mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
  95         mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
  96         mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
  97         mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
  98         mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
  99         mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
 100         mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
 101
 102         /* start SPI1 clock */
 103         __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
 104
 105         /* GPIO 57 */
 106         /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
 107         mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
 108
 109         /* SPI1 CS2 is free */
 110         ret = s6e63d6_init(&data);
 111         if (ret)
 112                 return ret;
 113
 114         /*
 115          * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
 116          * OLED display connected to a S6E63D6 SPI display controller in the
 117          * 18 bit RGB mode
 118          */
 119         s6e63d6_index(&data, 2);
 120         s6e63d6_param(&data, 0x0182);
 121         s6e63d6_index(&data, 3);
 122         s6e63d6_param(&data, 0x8130);
 123         s6e63d6_index(&data, 0x10);
 124         s6e63d6_param(&data, 0x0000);
 125         s6e63d6_index(&data, 5);
 126         s6e63d6_param(&data, 0x0001);
 127         s6e63d6_index(&data, 0x22);
 128 #endif
 129         return 0;
 130 }
 131 #endif
 132
 133 int checkboard (void)
 134 {
 135         printf("Board: Phytec phyCore i.MX31\n");
 136         return 0;
 137 }
 138
 139 int board_eth_init(bd_t *bis)
 140 {
 141         int rc = 0;
 142 #ifdef CONFIG_SMC911X
 143         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 144 #endif
 145         return rc;
 146 }