board/imx31_phycore/imx31_phycore.c

   1 /*
   2  *
   3  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24
  25 #include <common.h>
  26 #include <s6e63d6.h>
  27 #include <netdev.h>
  28 #include <asm/arch/mx31.h>
  29 #include <asm/arch/mx31-regs.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 int dram_init (void)
  34 {
  35         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  36         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  37
  38         return 0;
  39 }
  40
  41 int board_init (void)
  42 {
  43         __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
  44         __REG(CSCR_L(0)) = 0x10000d03;
  45         __REG(CSCR_A(0)) = 0x00720900;
  46
  47         __REG(CSCR_U(1)) = 0x0000df06; /* CS1: Network Controller */
  48         __REG(CSCR_L(1)) = 0x444a4541;
  49         __REG(CSCR_A(1)) = 0x44443302;
  50
  51         __REG(CSCR_U(4)) = 0x0000d843; /* CS4: SRAM */
  52         __REG(CSCR_L(4)) = 0x22252521;
  53         __REG(CSCR_A(4)) = 0x22220a00;
  54
  55         /* setup pins for UART1 */
  56         mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
  57         mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
  58         mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
  59         mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
  60
  61         /* setup pins for I2C2 (for EEPROM, RTC) */
  62         mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
  63         mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
  64
  65         gd->bd->bi_arch_number = MACH_TYPE_PCM037;      /* board id for linux */
  66         gd->bd->bi_boot_params = (0x80000100);          /* adress of boot parameters */
  67
  68         return 0;
  69 }
  70
  71 #ifdef BOARD_LATE_INIT
  72 int board_late_init(void)
  73 {
  74 #ifdef CONFIG_S6E63D6
  75         struct s6e63d6 data = {
  76                 /*
  77                  * See comment in mxc_spi.c::decode_cs() for .cs field format.
  78                  * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
  79                  * 2 of the SPI controller #1, since it is unused.
  80                  */
  81                 .cs = 2 | (57 << 8),
  82                 .bus = 0,
  83                 .id = 0,
  84         };
  85         int ret;
  86
  87         /* SPI1 */
  88         mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
  89         mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
  90         mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
  91         mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
  92         mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
  93         mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
  94         mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
  95
  96         /* start SPI1 clock */
  97         __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
  98
  99         /* GPIO 57 */
 100         /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
 101         mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
 102
 103         /* SPI1 CS2 is free */
 104         ret = s6e63d6_init(&data);
 105         if (ret)
 106                 return ret;
 107
 108         /*
 109          * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
 110          * OLED display connected to a S6E63D6 SPI display controller in the
 111          * 18 bit RGB mode
 112          */
 113         s6e63d6_index(&data, 2);
 114         s6e63d6_param(&data, 0x0182);
 115         s6e63d6_index(&data, 3);
 116         s6e63d6_param(&data, 0x8130);
 117         s6e63d6_index(&data, 0x10);
 118         s6e63d6_param(&data, 0x0000);
 119         s6e63d6_index(&data, 5);
 120         s6e63d6_param(&data, 0x0001);
 121         s6e63d6_index(&data, 0x22);
 122 #endif
 123         return 0;
 124 }
 125 #endif
 126
 127 int checkboard (void)
 128 {
 129         printf("Board: Phytec phyCore i.MX31\n");
 130         return 0;
 131 }
 132
 133 int board_eth_init(bd_t *bis)
 134 {
 135         int rc = 0;
 136 #ifdef CONFIG_SMC911X
 137         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 138 #endif
 139         return rc;
 140 }