board/incaip/lowlevel_init.S

   1 /*
   2  *  Memory sub-system initialization code for INCA-IP development board.
   3  *
   4  *  Copyright (c) 2003  Wolfgang Denk <wd@denx.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <asm/regdef.h>
  27
  28
  29 #define EBU_MODUL_BASE          0xB8000200
  30 #define EBU_CLC(value)          0x0000(value)
  31 #define EBU_CON(value)          0x0010(value)
  32 #define EBU_ADDSEL0(value)      0x0020(value)
  33 #define EBU_ADDSEL1(value)      0x0024(value)
  34 #define EBU_ADDSEL2(value)      0x0028(value)
  35 #define EBU_BUSCON0(value)      0x0060(value)
  36 #define EBU_BUSCON1(value)      0x0064(value)
  37 #define EBU_BUSCON2(value)      0x0068(value)
  38
  39 #define MC_MODUL_BASE           0xBF800000
  40 #define MC_ERRCAUSE(value)      0x0100(value)
  41 #define MC_ERRADDR(value)       0x0108(value)
  42 #define MC_IOGP(value)          0x0800(value)
  43 #define MC_SELFRFSH(value)      0x0A00(value)
  44 #define MC_CTRLENA(value)       0x1000(value)
  45 #define MC_MRSCODE(value)       0x1008(value)
  46 #define MC_CFGDW(value)         0x1010(value)
  47 #define MC_CFGPB0(value)        0x1018(value)
  48 #define MC_LATENCY(value)       0x1038(value)
  49 #define MC_TREFRESH(value)      0x1040(value)
  50
  51 #define CGU_MODUL_BASE          0xBF107000
  52 #define CGU_PLL1CR(value)       0x0008(value)
  53 #define CGU_DIVCR(value)        0x0010(value)
  54 #define CGU_MUXCR(value)        0x0014(value)
  55 #define CGU_PLL1SR(value)       0x000C(value)
  56
  57         .set    noreorder
  58
  59
  60 /*
  61  * void ebu_init(long)
  62  *
  63  * a0 has the clock value we are going to run at
  64  */
  65         .globl  ebu_init
  66         .ent    ebu_init
  67 ebu_init:
  68 __ebu_init:
  69
  70         li      t1, EBU_MODUL_BASE
  71         li      t2, 0xA0000041
  72         sw      t2, EBU_ADDSEL0(t1)
  73         li      t2, 0xA0800041
  74         sw      t2, EBU_ADDSEL2(t1)
  75         li      t2, 0xBE0000F1
  76         sw      t2, EBU_ADDSEL1(t1)
  77
  78         li      t3, 100000000
  79         beq     a0, t3, 1f
  80         nop
  81         li      t3, 133000000
  82         beq     a0, t3, 2f
  83         nop
  84         li      t3, 150000000
  85         beq     a0, t3, 2f
  86         nop
  87         b       3f
  88         nop
  89
  90         /* 100 MHz */
  91 1:
  92         li      t2, 0x8841417D
  93         sw      t2, EBU_BUSCON0(t1)
  94         sw      t2, EBU_BUSCON2(t1)
  95         li      t2, 0x684142BD
  96         b       3f
  97         sw      t2, EBU_BUSCON1(t1)     /* delay slot */
  98
  99         /* 133 or 150 MHz */
 100 2:
 101         li      t2, 0x8841417E
 102         sw      t2, EBU_BUSCON0(t1)
 103         sw      t2, EBU_BUSCON2(t1)
 104         li      t2, 0x684143FD
 105         sw      t2, EBU_BUSCON1(t1)
 106 3:
 107         jr      ra
 108         nop
 109
 110         .end    ebu_init
 111
 112
 113 /*
 114  * void cgu_init(long)
 115  *
 116  * a0 has the clock value
 117  */
 118         .globl  cgu_init
 119         .ent    cgu_init
 120 cgu_init:
 121 __cgu_init:
 122
 123         li      t1, CGU_MODUL_BASE
 124
 125         li      t3, 100000000
 126         beq     a0, t3, 1f
 127         nop
 128         li      t3, 133000000
 129         beq     a0, t3, 2f
 130         nop
 131         li      t3, 150000000
 132         beq     a0, t3, 3f
 133         nop
 134         b       5f
 135         nop
 136
 137         /* 100 MHz clock */
 138 1:
 139         li      t2, 0x80000014
 140         sw      t2, CGU_DIVCR(t1)
 141         li      t2, 0x80000000
 142         sw      t2, CGU_MUXCR(t1)
 143         li      t2, 0x800B0001
 144         b       5f
 145         sw      t2, CGU_PLL1CR(t1)      /* delay slot */
 146
 147         /* 133 MHz clock */
 148 2:
 149         li      t2, 0x80000054
 150         sw      t2, CGU_DIVCR(t1)
 151         li      t2, 0x80000000
 152         sw      t2, CGU_MUXCR(t1)
 153         li      t2, 0x800B0001
 154         b       5f
 155         sw      t2, CGU_PLL1CR(t1)      /* delay slot */
 156
 157         /* 150 MHz clock */
 158 3:
 159         li      t2, 0x80000017
 160         sw      t2, CGU_DIVCR(t1)
 161         li      t2, 0xC00B0001
 162         sw      t2, CGU_PLL1CR(t1)
 163         li      t3, 0x80000000
 164 4:
 165         lw      t2, CGU_PLL1SR(t1)
 166         and     t2, t2, t3
 167         beq     t2, zero, 4b
 168         nop
 169         li      t2, 0x80000001
 170         sw      t2, CGU_MUXCR(t1)
 171 5:
 172         jr      ra
 173         nop
 174
 175         .end    cgu_init
 176
 177
 178 /*
 179  * void sdram_init(long)
 180  *
 181  * a0 has the clock value
 182  */
 183         .globl  sdram_init
 184         .ent    sdram_init
 185 sdram_init:
 186 __sdram_init:
 187
 188         li      t1, MC_MODUL_BASE
 189
 190 #if 0
 191         /* Disable memory controller before changing any of its registers */
 192         sw      zero, MC_CTRLENA(t1)
 193 #endif
 194
 195         li      t2, 100000000
 196         beq     a0, t2, 1f
 197         nop
 198         li      t2, 133000000
 199         beq     a0, t2, 2f
 200         nop
 201         li      t2, 150000000
 202         beq     a0, t2, 3f
 203         nop
 204         b       5f
 205         nop
 206
 207         /* 100 MHz clock */
 208 1:
 209         /* Set clock ratio (clkrat=1:1, rddel=3) */
 210         li      t2, 0x00000003
 211         sw      t2, MC_IOGP(t1)
 212
 213         /* Set sdram refresh rate (4K/64ms @ 100MHz) */
 214         li      t2, 0x0000061A
 215         b       4f
 216         sw      t2, MC_TREFRESH(t1)
 217
 218         /* 133 MHz clock */
 219 2:
 220         /* Set clock ratio (clkrat=1:1, rddel=3) */
 221         li      t2, 0x00000003
 222         sw      t2, MC_IOGP(t1)
 223
 224         /* Set sdram refresh rate (4K/64ms @ 133MHz) */
 225         li      t2, 0x00000822
 226         b       4f
 227         sw      t2, MC_TREFRESH(t1)
 228
 229         /* 150 MHz clock */
 230 3:
 231         /* Set clock ratio (clkrat=3:2, rddel=4) */
 232         li      t2, 0x00000014
 233         sw      t2, MC_IOGP(t1)
 234
 235         /* Set sdram refresh rate (4K/64ms @ 150MHz) */
 236         li      t2, 0x00000927
 237         sw      t2, MC_TREFRESH(t1)
 238
 239 4:
 240         /* Clear Error log registers */
 241         sw      zero, MC_ERRCAUSE(t1)
 242         sw      zero, MC_ERRADDR(t1)
 243
 244         /* Clear Power-down registers */
 245         sw      zero, MC_SELFRFSH(t1)
 246
 247         /* Set CAS Latency */
 248         li      t2, 0x00000020          /* CL = 2 */
 249         sw      t2, MC_MRSCODE(t1)
 250
 251         /* Set word width to 16 bit */
 252         li      t2, 0x2
 253         sw      t2, MC_CFGDW(t1)
 254
 255         /* Set CS0 to SDRAM parameters */
 256         li      t2, 0x000014C9
 257         sw      t2, MC_CFGPB0(t1)
 258
 259         /* Set SDRAM latency parameters */
 260         li      t2, 0x00026325          /* BC PC100 */
 261         sw      t2, MC_LATENCY(t1)
 262
 263 5:
 264         /* Finally enable the controller */
 265         li      t2, 0x00000001
 266         sw      t2, MC_CTRLENA(t1)
 267
 268         jr      ra
 269         nop
 270
 271         .end    sdram_init
 272
 273
 274         .globl  lowlevel_init
 275         .ent    lowlevel_init
 276 lowlevel_init:
 277
 278         /* Disable Watchdog.
 279          */
 280         la      t9, disable_incaip_wdt
 281         jalr    t9
 282         nop
 283
 284         /* EBU, CGU and SDRAM Initialization.
 285          */
 286         li      a0, CPU_CLOCK_RATE
 287         move    t0, ra
 288
 289         /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
 290          * modify t0 and a0.
 291          */
 292         bal     __cgu_init
 293         nop
 294         bal     __ebu_init
 295         nop
 296         bal     __sdram_init
 297         nop
 298         move    ra, t0
 299
 300         jr      ra
 301         nop
 302
 303         .end    lowlevel_init