board/inka4x0/inka4x0.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * (C) Copyright 2004
   9  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <common.h>
  31 #include <mpc5xxx.h>
  32 #include <pci.h>
  33
  34 #if defined(CONFIG_MPC5200_DDR)
  35 #include "mt46v16m16-75.h"
  36 #else
  37 #include "mt48lc16m16a2-75.h"
  38 #endif
  39
  40 #ifndef CFG_RAMBOOT
  41 static void sdram_start (int hi_addr)
  42 {
  43         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  44
  45         /* unlock mode register */
  46         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  47         __asm__ volatile ("sync");
  48
  49         /* precharge all banks */
  50         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  51         __asm__ volatile ("sync");
  52
  53 #if SDRAM_DDR
  54         /* set mode register: extended mode */
  55         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  56         __asm__ volatile ("sync");
  57
  58         /* set mode register: reset DLL */
  59         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  60         __asm__ volatile ("sync");
  61 #endif
  62
  63         /* precharge all banks */
  64         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  65         __asm__ volatile ("sync");
  66
  67         /* auto refresh */
  68         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  69         __asm__ volatile ("sync");
  70
  71         /* set mode register */
  72         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  73         __asm__ volatile ("sync");
  74
  75         /* normal operation */
  76         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  77         __asm__ volatile ("sync");
  78 }
  79 #endif
  80
  81 /*
  82  * ATTENTION: Although partially referenced initdram does NOT make real use
  83  *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
  84  *            is something else than 0x00000000.
  85  */
  86
  87 long int initdram (int board_type)
  88 {
  89         ulong dramsize = 0;
  90 #ifndef CFG_RAMBOOT
  91         ulong test1, test2;
  92
  93         /* setup SDRAM chip selects */
  94         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
  95         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
  96         __asm__ volatile ("sync");
  97
  98         /* setup config registers */
  99         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 100         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 101         __asm__ volatile ("sync");
 102
 103 #if SDRAM_DDR
 104         /* set tap delay */
 105         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 106         __asm__ volatile ("sync");
 107 #endif
 108
 109         /* find RAM size using SDRAM CS0 only */
 110         sdram_start(0);
 111         test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
 112         sdram_start(1);
 113         test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
 114         if (test1 > test2) {
 115                 sdram_start(0);
 116                 dramsize = test1;
 117         } else {
 118                 dramsize = test2;
 119         }
 120
 121         /* memory smaller than 1MB is impossible */
 122         if (dramsize < (1 << 20)) {
 123                 dramsize = 0;
 124         }
 125
 126         /* set SDRAM CS0 size according to the amount of RAM found */
 127         if (dramsize > 0) {
 128                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
 129                         __builtin_ffs(dramsize >> 20) - 1;
 130         } else {
 131                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 132         }
 133
 134         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 135 #else /* CFG_RAMBOOT */
 136
 137         /* retrieve size of memory connected to SDRAM CS0 */
 138         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 139         if (dramsize >= 0x13) {
 140                 dramsize = (1 << (dramsize - 0x13)) << 20;
 141         } else {
 142                 dramsize = 0;
 143         }
 144
 145         /* retrieve size of memory connected to SDRAM CS1 */
 146         dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 147         if (dramsize2 >= 0x13) {
 148                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 149         } else {
 150                 dramsize2 = 0;
 151         }
 152
 153 #endif /* CFG_RAMBOOT */
 154
 155 /*      return dramsize + dramsize2; */
 156         return dramsize;
 157 }
 158
 159 int checkboard (void)
 160 {
 161         puts ("Board: INKA 4X0\n");
 162         return 0;
 163 }
 164
 165 void flash_preinit(void)
 166 {
 167         /*
 168          * Now, when we are in RAM, enable flash write
 169          * access for detection process.
 170          * Note that CS_BOOT cannot be cleared when
 171          * executing in flash.
 172          */
 173         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 174 }
 175
 176 #define GPIO_WKUP_7     0x80000000UL
 177 #define GPIO_PSC3_9     0x04000000UL
 178
 179 int misc_init_f (void)
 180 {
 181         uchar tmp[10];
 182         int i, br;
 183
 184         i = getenv_r("brightness", tmp, sizeof(tmp));
 185         br = (i > 0)
 186                 ? (int) simple_strtoul (tmp, NULL, 10)
 187                 : CFG_BRIGHTNESS;
 188         if (br > 255)
 189                 br = 255;
 190
 191         /* Initialize GPIO output pins.
 192          */
 193         /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
 194         *(vu_long *)MPC5XXX_GPT0_ENABLE =
 195         *(vu_long *)MPC5XXX_GPT1_ENABLE =
 196         *(vu_long *)MPC5XXX_GPT2_ENABLE =
 197         *(vu_long *)MPC5XXX_GPT3_ENABLE =
 198         *(vu_long *)MPC5XXX_GPT4_ENABLE =
 199         *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;
 200
 201         /* Configure GPT7 as PWM timer, 1kHz, no ints. */
 202         *(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
 203         *(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe;
 204         *(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16);
 205         *(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */
 206
 207         /* Configure PSC3_6,7 as GPIO output */
 208         *(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
 209         *(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
 210
 211         /* Configure PSC3_8 as GPIO output, no interrupt */
 212         *(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
 213         *(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
 214         *(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
 215
 216         /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
 217         *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
 218         *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
 219
 220         /* Set LR mirror bit because it is low-active */
 221         *(vu_long *)MPC5XXX_WU_GPIO_DATA    |= GPIO_WKUP_7;
 222         /*
 223          * Reset Coral-P graphics controller
 224          */
 225         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
 226         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC3_9;
 227         *(vu_long *) MPC5XXX_WU_GPIO_DATA   |= GPIO_PSC3_9;
 228         return 0;
 229 }
 230
 231 #ifdef  CONFIG_PCI
 232 static struct pci_controller hose;
 233
 234 extern void pci_mpc5xxx_init(struct pci_controller *);
 235
 236 void pci_init_board(void)
 237 {
 238         pci_mpc5xxx_init(&hose);
 239 }
 240 #endif
 241
 242 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
 243
 244 #define GPIO_PSC1_4     0x01000000UL
 245
 246 void init_ide_reset (void)
 247 {
 248         debug ("init_ide_reset\n");
 249
 250         /* Configure PSC1_4 as GPIO output for ATA reset */
 251         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 252         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 253         /* Deassert reset */
 254         *(vu_long *) MPC5XXX_WU_GPIO_DATA   |= GPIO_PSC1_4;
 255 }
 256
 257 void ide_set_reset (int idereset)
 258 {
 259         debug ("ide_reset(%d)\n", idereset);
 260
 261         if (idereset) {
 262                 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
 263                 /* Make a delay. MPC5200 spec says 25 usec min */
 264                 udelay(500000);
 265         } else {
 266                 *(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
 267         }
 268 }
 269 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */