2 * (C) Copyright 2008-2009
3 * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
6 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
9 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
12 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
14 * (C) Copyright 2003-2004
15 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
17 * SPDX-License-Identifier: GPL-2.0+
25 #if defined(CONFIG_DDR_MT46V16M16)
26 #include "mt46v16m16-75.h"
27 #elif defined(CONFIG_SDR_MT48LC16M16A2)
28 #include "mt48lc16m16a2-75.h"
29 #elif defined(CONFIG_DDR_MT46V32M16)
30 #include "mt46v32m16.h"
31 #elif defined(CONFIG_DDR_HYB25D512160BF)
32 #include "hyb25d512160bf.h"
33 #elif defined(CONFIG_DDR_K4H511638C)
34 #include "k4h511638c.h"
36 #error "INKA4x0 SDRAM: invalid chip type specified!"
39 #ifndef CONFIG_SYS_RAMBOOT
40 static void sdram_start (int hi_addr
)
42 volatile struct mpc5xxx_sdram
*sdram
=
43 (struct mpc5xxx_sdram
*)MPC5XXX_SDRAM
;
44 long hi_addr_bit
= hi_addr
? 0x01000000 : 0;
46 /* unlock mode register */
47 out_be32(&sdram
->ctrl
, SDRAM_CONTROL
| 0x80000000 | hi_addr_bit
);
49 /* precharge all banks */
50 out_be32(&sdram
->ctrl
, SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
);
53 /* set mode register: extended mode */
54 out_be32(&sdram
->mode
, SDRAM_EMODE
);
56 /* set mode register: reset DLL */
57 out_be32(&sdram
->mode
, SDRAM_MODE
| 0x04000000);
60 /* precharge all banks */
61 out_be32(&sdram
->ctrl
, SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
);
64 out_be32(&sdram
->ctrl
, SDRAM_CONTROL
| 0x80000004 | hi_addr_bit
);
66 /* set mode register */
67 out_be32(&sdram
->mode
, SDRAM_MODE
);
69 /* normal operation */
70 out_be32(&sdram
->ctrl
, SDRAM_CONTROL
| hi_addr_bit
);
75 * ATTENTION: Although partially referenced initdram does NOT make real use
76 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
77 * is something else than 0x00000000.
80 phys_size_t
initdram(void)
82 volatile struct mpc5xxx_mmap_ctl
*mm
=
83 (struct mpc5xxx_mmap_ctl
*) CONFIG_SYS_MBAR
;
84 volatile struct mpc5xxx_cdm
*cdm
=
85 (struct mpc5xxx_cdm
*) MPC5XXX_CDM
;
86 volatile struct mpc5xxx_sdram
*sdram
=
87 (struct mpc5xxx_sdram
*) MPC5XXX_SDRAM
;
89 #ifndef CONFIG_SYS_RAMBOOT
92 /* setup SDRAM chip selects */
93 out_be32(&mm
->sdram0
, 0x0000001c); /* 512MB at 0x0 */
94 out_be32(&mm
->sdram1
, 0x40000000); /* disabled */
96 /* setup config registers */
97 out_be32(&sdram
->config1
, SDRAM_CONFIG1
);
98 out_be32(&sdram
->config2
, SDRAM_CONFIG2
);
102 out_be32(&cdm
->porcfg
, SDRAM_TAPDELAY
);
105 /* find RAM size using SDRAM CS0 only */
107 test1
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x20000000);
109 test2
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x20000000);
117 /* memory smaller than 1MB is impossible */
118 if (dramsize
< (1 << 20)) {
122 /* set SDRAM CS0 size according to the amount of RAM found */
124 out_be32(&mm
->sdram0
, 0x13 +
125 __builtin_ffs(dramsize
>> 20) - 1);
127 out_be32(&mm
->sdram0
, 0); /* disabled */
130 out_be32(&mm
->sdram1
, dramsize
); /* disabled */
131 #else /* CONFIG_SYS_RAMBOOT */
133 /* retrieve size of memory connected to SDRAM CS0 */
134 dramsize
= in_be32(&mm
->sdram0
) & 0xFF;
135 if (dramsize
>= 0x13) {
136 dramsize
= (1 << (dramsize
- 0x13)) << 20;
140 #endif /* CONFIG_SYS_RAMBOOT */
145 int checkboard (void)
147 puts ("Board: INKA 4X0\n");
151 void flash_preinit(void)
153 volatile struct mpc5xxx_lpb
*lpb
= (struct mpc5xxx_lpb
*)MPC5XXX_LPB
;
156 * Now, when we are in RAM, enable flash write
157 * access for detection process.
158 * Note that CS_BOOT (CS0) cannot be cleared when
159 * executing in flash.
161 clrbits_be32(&lpb
->cs0_cfg
, 0x1); /* clear RO */
164 int misc_init_f (void)
166 volatile struct mpc5xxx_gpio
*gpio
=
167 (struct mpc5xxx_gpio
*) MPC5XXX_GPIO
;
168 volatile struct mpc5xxx_wu_gpio
*wu_gpio
=
169 (struct mpc5xxx_wu_gpio
*)MPC5XXX_WU_GPIO
;
170 volatile struct mpc5xxx_gpt
*gpt
;
174 i
= getenv_f("brightness", tmp
, sizeof(tmp
));
176 ? (int) simple_strtoul (tmp
, NULL
, 10)
177 : CONFIG_SYS_BRIGHTNESS
;
181 /* Initialize GPIO output pins.
183 /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
184 for (i
= 0; i
<= 5; i
++) {
185 gpt
= (struct mpc5xxx_gpt
*)(MPC5XXX_GPT
+ (i
* 0x10));
186 out_be32(&gpt
->emsr
, 0x34);
189 /* Configure GPT7 as PWM timer, 1kHz, no ints. */
190 gpt
= (struct mpc5xxx_gpt
*)(MPC5XXX_GPT
+ (7 * 0x10));
191 out_be32(&gpt
->emsr
, 0); /* Disable */
192 out_be32(&gpt
->cir
, 0x020000fe);
193 out_be32(&gpt
->pwmcr
, (br
<< 16));
194 out_be32(&gpt
->emsr
, 0x3); /* Enable PWM mode and start */
196 /* Configure PSC3_6,7 as GPIO output */
197 setbits_be32(&gpio
->simple_gpioe
, MPC5XXX_GPIO_SIMPLE_PSC3_6
|
198 MPC5XXX_GPIO_SIMPLE_PSC3_7
);
199 setbits_be32(&gpio
->simple_ddr
, MPC5XXX_GPIO_SIMPLE_PSC3_6
|
200 MPC5XXX_GPIO_SIMPLE_PSC3_7
);
202 /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
203 setbits_8(&wu_gpio
->enable
, MPC5XXX_GPIO_WKUP_6
|
204 MPC5XXX_GPIO_WKUP_7
|
205 MPC5XXX_GPIO_WKUP_PSC3_9
);
206 setbits_8(&wu_gpio
->ddr
, MPC5XXX_GPIO_WKUP_6
|
207 MPC5XXX_GPIO_WKUP_7
|
208 MPC5XXX_GPIO_WKUP_PSC3_9
);
210 /* Set LR mirror bit because it is low-active */
211 setbits_8(&wu_gpio
->dvo
, MPC5XXX_GPIO_WKUP_7
);
213 /* Reset Coral-P graphics controller */
214 setbits_8(&wu_gpio
->dvo
, MPC5XXX_GPIO_WKUP_PSC3_9
);
216 /* Enable display backlight */
217 clrbits_8(&gpio
->sint_inten
, MPC5XXX_GPIO_SINT_PSC3_8
);
218 setbits_8(&gpio
->sint_gpioe
, MPC5XXX_GPIO_SINT_PSC3_8
);
219 setbits_8(&gpio
->sint_ddr
, MPC5XXX_GPIO_SINT_PSC3_8
);
220 setbits_8(&gpio
->sint_dvo
, MPC5XXX_GPIO_SINT_PSC3_8
);
223 * Configure three wire serial interface to RTC (PSC1_4,
224 * PSC2_4, PSC3_4, PSC3_5)
226 setbits_8(&wu_gpio
->enable
, MPC5XXX_GPIO_WKUP_PSC1_4
|
227 MPC5XXX_GPIO_WKUP_PSC2_4
);
228 setbits_8(&wu_gpio
->ddr
, MPC5XXX_GPIO_WKUP_PSC1_4
|
229 MPC5XXX_GPIO_WKUP_PSC2_4
);
230 clrbits_8(&wu_gpio
->dvo
, MPC5XXX_GPIO_WKUP_PSC1_4
);
231 clrbits_8(&gpio
->sint_inten
, MPC5XXX_GPIO_SINT_PSC3_4
|
232 MPC5XXX_GPIO_SINT_PSC3_5
);
233 setbits_8(&gpio
->sint_gpioe
, MPC5XXX_GPIO_SINT_PSC3_4
|
234 MPC5XXX_GPIO_SINT_PSC3_5
);
235 setbits_8(&gpio
->sint_ddr
, MPC5XXX_GPIO_SINT_PSC3_5
);
236 clrbits_8(&gpio
->sint_dvo
, MPC5XXX_GPIO_SINT_PSC3_5
);
242 static struct pci_controller hose
;
244 extern void pci_mpc5xxx_init(struct pci_controller
*);
246 void pci_init_board(void)
248 pci_mpc5xxx_init(&hose
);