board/inka4x0/inka4x0.c

   1 /*
   2  * (C) Copyright 2008-2009
   3  * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
   4  *
   5  * (C) Copyright 2009
   6  * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
   7  *
   8  * (C) Copyright 2004
   9  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  10  *
  11  * (C) Copyright 2004
  12  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  13  *
  14  * (C) Copyright 2003-2004
  15  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  */
  35
  36 #include <common.h>
  37 #include <mpc5xxx.h>
  38 #include <pci.h>
  39
  40 #if defined(CONFIG_DDR_MT46V16M16)
  41 #include "mt46v16m16-75.h"
  42 #elif defined(CONFIG_SDR_MT48LC16M16A2)
  43 #include "mt48lc16m16a2-75.h"
  44 #elif defined(CONFIG_DDR_MT46V32M16)
  45 #include "mt46v32m16.h"
  46 #elif defined(CONFIG_DDR_HYB25D512160BF)
  47 #include "hyb25d512160bf.h"
  48 #elif defined(CONFIG_DDR_K4H511638C)
  49 #include "k4h511638c.h"
  50 #else
  51 #error "INKA4x0 SDRAM: invalid chip type specified!"
  52 #endif
  53
  54 #ifndef CONFIG_SYS_RAMBOOT
  55 static void sdram_start (int hi_addr)
  56 {
  57         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  58
  59         /* unlock mode register */
  60         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  61         __asm__ volatile ("sync");
  62
  63         /* precharge all banks */
  64         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  65         __asm__ volatile ("sync");
  66
  67 #if SDRAM_DDR
  68         /* set mode register: extended mode */
  69         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  70         __asm__ volatile ("sync");
  71
  72         /* set mode register: reset DLL */
  73         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  74         __asm__ volatile ("sync");
  75 #endif
  76
  77         /* precharge all banks */
  78         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  79         __asm__ volatile ("sync");
  80
  81         /* auto refresh */
  82         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  83         __asm__ volatile ("sync");
  84
  85         /* set mode register */
  86         *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  87         __asm__ volatile ("sync");
  88
  89         /* normal operation */
  90         *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  91         __asm__ volatile ("sync");
  92 }
  93 #endif
  94
  95 /*
  96  * ATTENTION: Although partially referenced initdram does NOT make real use
  97  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  98  *            is something else than 0x00000000.
  99  */
 100
 101 phys_size_t initdram (int board_type)
 102 {
 103         ulong dramsize = 0;
 104 #ifndef CONFIG_SYS_RAMBOOT
 105         long test1, test2;
 106
 107         /* setup SDRAM chip selects */
 108         *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
 109         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
 110         __asm__ volatile ("sync");
 111
 112         /* setup config registers */
 113         *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 114         *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 115         __asm__ volatile ("sync");
 116
 117 #if SDRAM_DDR
 118         /* set tap delay */
 119         *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 120         __asm__ volatile ("sync");
 121 #endif
 122
 123         /* find RAM size using SDRAM CS0 only */
 124         sdram_start(0);
 125         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 126         sdram_start(1);
 127         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 128         if (test1 > test2) {
 129                 sdram_start(0);
 130                 dramsize = test1;
 131         } else {
 132                 dramsize = test2;
 133         }
 134
 135         /* memory smaller than 1MB is impossible */
 136         if (dramsize < (1 << 20)) {
 137                 dramsize = 0;
 138         }
 139
 140         /* set SDRAM CS0 size according to the amount of RAM found */
 141         if (dramsize > 0) {
 142                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
 143                         __builtin_ffs(dramsize >> 20) - 1;
 144         } else {
 145                 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 146         }
 147
 148         *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 149 #else /* CONFIG_SYS_RAMBOOT */
 150
 151         /* retrieve size of memory connected to SDRAM CS0 */
 152         dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 153         if (dramsize >= 0x13) {
 154                 dramsize = (1 << (dramsize - 0x13)) << 20;
 155         } else {
 156                 dramsize = 0;
 157         }
 158 #endif /* CONFIG_SYS_RAMBOOT */
 159
 160         return dramsize;
 161 }
 162
 163 int checkboard (void)
 164 {
 165         puts ("Board: INKA 4X0\n");
 166         return 0;
 167 }
 168
 169 void flash_preinit(void)
 170 {
 171         /*
 172          * Now, when we are in RAM, enable flash write
 173          * access for detection process.
 174          * Note that CS_BOOT cannot be cleared when
 175          * executing in flash.
 176          */
 177         *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 178 }
 179
 180 int misc_init_r (void) {
 181         extern int inkadiag_init_r (void);
 182
 183         /*
 184          * The command table used for the subcommands of inkadiag
 185          * needs to be relocated manually.
 186          */
 187         return inkadiag_init_r();
 188 }
 189
 190 int misc_init_f (void)
 191 {
 192         char tmp[10];
 193         int i, br;
 194
 195         i = getenv_r("brightness", tmp, sizeof(tmp));
 196         br = (i > 0)
 197                 ? (int) simple_strtoul (tmp, NULL, 10)
 198                 : CONFIG_SYS_BRIGHTNESS;
 199         if (br > 255)
 200                 br = 255;
 201
 202         /* Initialize GPIO output pins.
 203          */
 204         /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
 205         *(vu_long *)MPC5XXX_GPT0_ENABLE =
 206         *(vu_long *)MPC5XXX_GPT1_ENABLE =
 207         *(vu_long *)MPC5XXX_GPT2_ENABLE =
 208         *(vu_long *)MPC5XXX_GPT3_ENABLE =
 209         *(vu_long *)MPC5XXX_GPT4_ENABLE =
 210         *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;
 211
 212         /* Configure GPT7 as PWM timer, 1kHz, no ints. */
 213         *(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
 214         *(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe;
 215         *(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16);
 216         *(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */
 217
 218         /* Configure PSC3_6,7 as GPIO output */
 219         *(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
 220         *(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
 221
 222         /* Configure PSC3_8 as GPIO output, no interrupt */
 223         *(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
 224         *(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
 225         *(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
 226
 227         /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
 228         *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
 229         *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
 230
 231         /* Set LR mirror bit because it is low-active */
 232         *(vu_long *) MPC5XXX_WU_GPIO_DATA_O    |= GPIO_WKUP_7;
 233         /*
 234          * Reset Coral-P graphics controller
 235          */
 236         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
 237         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC3_9;
 238         *(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC3_9;
 239         return 0;
 240 }
 241
 242 #ifdef  CONFIG_PCI
 243 static struct pci_controller hose;
 244
 245 extern void pci_mpc5xxx_init(struct pci_controller *);
 246
 247 void pci_init_board(void)
 248 {
 249         pci_mpc5xxx_init(&hose);
 250 }
 251 #endif
 252
 253 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 254
 255 void init_ide_reset (void)
 256 {
 257         debug ("init_ide_reset\n");
 258
 259         /* Configure PSC1_4 as GPIO output for ATA reset */
 260         *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 261         *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 262         /* Deassert reset */
 263         *(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
 264 }
 265
 266 void ide_set_reset (int idereset)
 267 {
 268         debug ("ide_reset(%d)\n", idereset);
 269
 270         if (idereset) {
 271                 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
 272                 /* Make a delay. MPC5200 spec says 25 usec min */
 273                 udelay(500000);
 274         } else {
 275                 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
 276         }
 277 }
 278 #endif