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[people/ms/u-boot.git] / board / integratorap / integratorap.c
1 /*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * (C) Copyright 2004
14 * ARM Ltd.
15 * Philippe Robin, <philippe.robin@arm.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36 #include <common.h>
37
38 #ifdef CONFIG_PCI
39 # include <pci.h>
40 #endif
41
42 void flash__init (void);
43 void ether__init (void);
44 void peripheral_power_enable (void);
45
46 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
47 void show_boot_progress(int progress)
48 {
49 printf("Boot reached stage %d\n", progress);
50 }
51 #endif
52
53 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
54
55 static inline void delay (unsigned long loops)
56 {
57 __asm__ volatile ("1:\n"
58 "subs %0, %1, #1\n"
59 "bne 1b":"=r" (loops):"0" (loops));
60 }
61
62 /*
63 * Miscellaneous platform dependent initialisations
64 */
65
66 int board_init (void)
67 {
68 DECLARE_GLOBAL_DATA_PTR;
69
70 /* arch number of Integrator Board */
71 gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
72
73 /* adress of boot parameters */
74 gd->bd->bi_boot_params = 0x00000100;
75
76 gd->flags = 0;
77
78 icache_enable ();
79
80 flash__init ();
81 return 0;
82 }
83
84
85 int misc_init_r (void)
86 {
87 #ifdef CONFIG_PCI
88 pci_init();
89 #endif
90 setenv("verify", "n");
91 return (0);
92 }
93
94 /*
95 * Initialize PCI Devices, report devices found.
96 */
97 #ifdef CONFIG_PCI
98
99 #ifndef CONFIG_PCI_PNP
100
101 static struct pci_config_table pci_integrator_config_table[] = {
102 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
103 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
104 PCI_ENET0_MEMADDR,
105 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
106 { }
107 };
108 #endif
109
110 /* V3 access routines */
111 #define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
112 #define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
113
114 #define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
115 #define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
116
117 /* Compute address necessary to access PCI config space for the given */
118 /* bus and device. */
119 #define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({ \
120 unsigned int __address, __devicebit; \
121 unsigned short __mapaddress; \
122 unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */ \
123 \
124 if (__bus == 0) { \
125 /* local bus segment so need a type 0 config cycle */ \
126 /* build the PCI configuration "address" with one-hot in A31-A11 */ \
127 __address = PCI_CONFIG_BASE; \
128 __address |= ((__devfn & 0x07) << 8); \
129 __address |= __offset & 0xFF; \
130 __mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \
131 __devicebit = (1 << (__dev + 11)); \
132 \
133 if ((__devicebit & 0xFF000000) != 0) { \
134 /* high order bits are handled by the MAP register */ \
135 __mapaddress |= (__devicebit >> 16); \
136 } else { \
137 /* low order bits handled directly in the address */ \
138 __address |= __devicebit; \
139 } \
140 } else { /* bus !=0 */ \
141 /* not the local bus segment so need a type 1 config cycle */ \
142 /* A31-A24 are don't care (so clear to 0) */ \
143 __mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \
144 __address = PCI_CONFIG_BASE; \
145 __address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \
146 __address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \
147 __address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number */ \
148 __address |= __offset & 0xFF; /* bits 7..0 = register number */ \
149 } \
150 _V3Write16 (V3_LB_MAP1, __mapaddress); \
151 __address; \
152 })
153
154 /* _V3OpenConfigWindow - open V3 configuration window */
155 #define _V3OpenConfigWindow() { \
156 /* Set up base0 to see all 512Mbytes of memory space (not */ \
157 /* prefetchable), this frees up base1 for re-use by configuration*/ \
158 /* memory */ \
159 \
160 _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
161 0x90 | V3_LB_BASE_M_ENABLE)); \
162 /* Set up base1 to point into configuration space, note that MAP1 */ \
163 /* register is set up by pciMakeConfigAddress(). */ \
164 \
165 _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) | \
166 0x40 | V3_LB_BASE_M_ENABLE)); \
167 }
168
169 /* _V3CloseConfigWindow - close V3 configuration window */
170 #define _V3CloseConfigWindow() { \
171 /* Reassign base1 for use by prefetchable PCI memory */ \
172 _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \
173 | 0x84 | V3_LB_BASE_M_ENABLE)); \
174 _V3Write16 (V3_LB_MAP1, \
175 (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006); \
176 \
177 /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \
178 \
179 _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
180 0x80 | V3_LB_BASE_M_ENABLE)); \
181 }
182
183 static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev,
184 int offset, unsigned char *val)
185 {
186 _V3OpenConfigWindow ();
187 *val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
188 PCI_FUNC (dev),
189 offset);
190 _V3CloseConfigWindow ();
191
192 return 0;
193 }
194
195 static int pci_integrator_read__word (struct pci_controller *hose,
196 pci_dev_t dev, int offset,
197 unsigned short *val)
198 {
199 _V3OpenConfigWindow ();
200 *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
201 PCI_FUNC (dev),
202 offset);
203 _V3CloseConfigWindow ();
204
205 return 0;
206 }
207
208 static int pci_integrator_read_dword (struct pci_controller *hose,
209 pci_dev_t dev, int offset,
210 unsigned int *val)
211 {
212 _V3OpenConfigWindow ();
213 *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
214 PCI_FUNC (dev),
215 offset);
216 *val |= (*(volatile unsigned int *)
217 PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev),
218 (offset + 2))) << 16;
219 _V3CloseConfigWindow ();
220
221 return 0;
222 }
223
224 static int pci_integrator_write_byte (struct pci_controller *hose,
225 pci_dev_t dev, int offset,
226 unsigned char val)
227 {
228 _V3OpenConfigWindow ();
229 *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
230 PCI_FUNC (dev),
231 offset) = val;
232 _V3CloseConfigWindow ();
233
234 return 0;
235 }
236
237 static int pci_integrator_write_word (struct pci_controller *hose,
238 pci_dev_t dev, int offset,
239 unsigned short val)
240 {
241 _V3OpenConfigWindow ();
242 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
243 PCI_FUNC (dev),
244 offset) = val;
245 _V3CloseConfigWindow ();
246
247 return 0;
248 }
249
250 static int pci_integrator_write_dword (struct pci_controller *hose,
251 pci_dev_t dev, int offset,
252 unsigned int val)
253 {
254 _V3OpenConfigWindow ();
255 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
256 PCI_FUNC (dev),
257 offset) = (val & 0xFFFF);
258 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
259 PCI_FUNC (dev),
260 (offset + 2)) = ((val >> 16) & 0xFFFF);
261 _V3CloseConfigWindow ();
262
263 return 0;
264 }
265 /******************************
266 * PCI initialisation
267 ******************************/
268
269 struct pci_controller integrator_hose = {
270 #ifndef CONFIG_PCI_PNP
271 config_table: pci_integrator_config_table,
272 #endif
273 };
274
275 void pci_init_board (void)
276 {
277 volatile int i, j;
278 struct pci_controller *hose = &integrator_hose;
279
280 /* setting this register will take the V3 out of reset */
281
282 *(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1;
283
284 /* wait a few usecs to settle the device and the PCI bus */
285
286 for (i = 0; i < 100; i++)
287 j = i + 1;
288
289 /* Now write the Base I/O Address Word to V3_BASE + 0x6C */
290
291 *(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) =
292 (unsigned short) (V3_BASE >> 16);
293
294 do {
295 *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA;
296 *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) =
297 0x55;
298 } while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA
299 || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA +
300 4) != 0x55);
301
302 /* Make sure that V3 register access is not locked, if it is, unlock it */
303
304 if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &
305 V3_SYSTEM_M_LOCK)
306 == V3_SYSTEM_M_LOCK)
307 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F;
308
309 /* Ensure that the slave accesses from PCI are disabled while we */
310 /* setup windows */
311
312 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &=
313 ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
314
315 /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
316
317 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &=
318 ~V3_SYSTEM_M_RST_OUT;
319
320 /* Make all accesses from PCI space retry until we're ready for them */
321
322 *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |=
323 V3_PCI_CFG_M_RETRY_EN;
324
325 /* Set up any V3 PCI Configuration Registers that we absolutely have to */
326 /* LB_CFG controls Local Bus protocol. */
327 /* Enable LocalBus byte strobes for READ accesses too. */
328 /* set bit 7 BE_IMODE and bit 6 BE_OMODE */
329
330 *(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0;
331
332 /* PCI_CMD controls overall PCI operation. */
333 /* Enable PCI bus master. */
334
335 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04;
336
337 /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */
338
339 *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) =
340 (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M |
341 V3_PCI_MAP_M_REG_EN |
342 V3_PCI_MAP_M_ENABLE);
343
344 /* PCI_BASE0 is the PCI address of the start of the window */
345
346 *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) =
347 INTEGRATOR_BOOT_ROM_BASE;
348
349 /* PCI_MAP1 is LOCAL address of the start of the window */
350
351 *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) =
352 (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M |
353 V3_PCI_MAP_M_REG_EN |
354 V3_PCI_MAP_M_ENABLE);
355
356 /* PCI_BASE1 is the PCI address of the start of the window */
357
358 *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) =
359 INTEGRATOR_HDR0_SDRAM_BASE;
360
361 /* Set up the windows from local bus memory into PCI configuration, */
362 /* I/O and Memory. */
363 /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
364
365 *(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) =
366 ((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
367 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0;
368
369 /* PCI Configuration, use LB_BASE1/LB_MAP1. */
370
371 /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
372 /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
373 /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
374
375 *(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) =
376 INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
377
378 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) =
379 ((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
380
381 /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
382
383 *(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) =
384 INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
385
386 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) =
387 (((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
388
389 /* Allow accesses to PCI Configuration space */
390 /* and set up A1, A0 for type 1 config cycles */
391
392 *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) =
393 ((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) &
394 ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) |
395 V3_PCI_CFG_M_AD_LOW0;
396
397 /* now we can allow in PCI MEMORY accesses */
398
399 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) =
400 (*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) |
401 V3_COMMAND_M_MEM_EN;
402
403 /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
404 /* initialise and lock the V3 system register so that no one else */
405 /* can play with it */
406
407 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
408 (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
409 V3_SYSTEM_M_RST_OUT;
410
411 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
412 (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
413 V3_SYSTEM_M_LOCK;
414
415 /*
416 * Register the hose
417 */
418 hose->first_busno = 0;
419 hose->last_busno = 0xff;
420
421 /* System memory space */
422 pci_set_region (hose->regions + 0,
423 0x00000000, 0x40000000, 0x01000000,
424 PCI_REGION_MEM | PCI_REGION_MEMORY);
425
426 /* PCI Memory - config space */
427 pci_set_region (hose->regions + 1,
428 0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM);
429
430 /* PCI V3 regs */
431 pci_set_region (hose->regions + 2,
432 0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM);
433
434 /* PCI I/O space */
435 pci_set_region (hose->regions + 3,
436 0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO);
437
438 pci_set_ops (hose,
439 pci_integrator_read_byte,
440 pci_integrator_read__word,
441 pci_integrator_read_dword,
442 pci_integrator_write_byte,
443 pci_integrator_write_word, pci_integrator_write_dword);
444
445 hose->region_count = 4;
446
447 pci_register_hose (hose);
448
449 pciauto_config_init (hose);
450 pciauto_config_device (hose, 0);
451
452 hose->last_busno = pci_hose_scan (hose);
453 }
454 #endif
455
456 /******************************
457 Routine:
458 Description:
459 ******************************/
460 void flash__init (void)
461 {
462 }
463 /*************************************************************
464 Routine:ether__init
465 Description: take the Ethernet controller out of reset and wait
466 for the EEPROM load to complete.
467 *************************************************************/
468 void ether__init (void)
469 {
470 }
471
472 /******************************
473 Routine:
474 Description:
475 ******************************/
476 int dram_init (void)
477 {
478 return 0;
479 }
480
481 /* The Integrator/AP timer1 is clocked at 24MHz
482 * can be divided by 16 or 256
483 * and is a 16-bit counter
484 */
485 /* U-Boot expects a 32 bit timer running at CFG_HZ*/
486 static ulong timestamp; /* U-Boot ticks since startup */
487 static ulong total_count = 0; /* Total timer count */
488 static ulong lastdec; /* Timer reading at last call */
489 static ulong div_clock = 256; /* Divisor applied to the timer clock */
490 static ulong div_timer = 1; /* Divisor to convert timer reading
491 * change to U-Boot ticks
492 */
493 /* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */
494
495 #define TIMER_LOAD_VAL 0x0000FFFFL
496 #define READ_TIMER ((*(volatile ulong *)(CFG_TIMERBASE+4)) & 0x0000FFFFL)
497
498 /* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec
499 * - unless otherwise stated
500 */
501
502 /* starts a counter
503 * - the Integrator/AP timer issues an interrupt
504 * each time it reaches zero
505 */
506 int interrupt_init (void)
507 {
508 /* Load timer with initial value */
509 *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
510 /* Set timer to be
511 * enabled 1
512 * free-running 0
513 * XX 00
514 * divider 256 10
515 * XX 00
516 */
517 *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x00000088;
518 total_count = 0;
519 /* init the timestamp and lastdec value */
520 reset_timer_masked();
521
522 div_timer = CFG_HZ_CLOCK / CFG_HZ;
523 div_timer /= div_clock;
524
525 return (0);
526 }
527
528 /*
529 * timer without interrupts
530 */
531 void reset_timer (void)
532 {
533 reset_timer_masked ();
534 }
535
536 ulong get_timer (ulong base_ticks)
537 {
538 return get_timer_masked () - base_ticks;
539 }
540
541 void set_timer (ulong ticks)
542 {
543 timestamp = ticks;
544 total_count = ticks * div_timer;
545 reset_timer_masked();
546 }
547
548 /* delay x useconds */
549 void udelay (unsigned long usec)
550 {
551 ulong tmo, tmp;
552
553 /* Convert to U-Boot ticks */
554 tmo = usec * CFG_HZ;
555 tmo /= (1000000L);
556
557 tmp = get_timer_masked(); /* get current timestamp */
558 tmo += tmp; /* wake up timestamp */
559
560 while (get_timer_masked () < tmo)/* loop till event */
561 {
562 /*NOP*/;
563 }
564 }
565
566 void reset_timer_masked (void)
567 {
568 /* reset time */
569 lastdec = READ_TIMER; /* capture current decrementer value */
570 timestamp = 0; /* start "advancing" time stamp from 0 */
571 }
572
573 /* converts the timer reading to U-Boot ticks */
574 /* the timestamp is the number of ticks since reset */
575 /* This routine does not detect wraps unless called regularly
576 ASSUMES a call at least every 16 seconds to detect every reload */
577 ulong get_timer_masked (void)
578 {
579 ulong now = READ_TIMER; /* current count */
580
581 if(now > lastdec)
582 {
583 /* Must have wrapped */
584 total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
585 } else {
586 total_count += lastdec - now;
587 }
588 lastdec = now;
589 timestamp = total_count/div_timer;
590
591 return timestamp;
592 }
593
594 /* waits specified delay value and resets timestamp */
595 void udelay_masked (unsigned long usec)
596 {
597 udelay(usec);
598 }
599
600 /*
601 * This function is derived from PowerPC code (read timebase as long long).
602 * On ARM it just returns the timer value.
603 */
604 unsigned long long get_ticks(void)
605 {
606 return get_timer(0);
607 }
608
609 /*
610 * Return the timebase clock frequency
611 * i.e. how often the timer decrements
612 */
613 ulong get_tbclk (void)
614 {
615 return CFG_HZ_CLOCK/div_clock;
616 }
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