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OMAP3: Add Zoom1 board support
[people/ms/u-boot.git] / board / integratorap / integratorap.c
1 /*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * (C) Copyright 2004
14 * ARM Ltd.
15 * Philippe Robin, <philippe.robin@arm.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36 #include <common.h>
37
38 #ifdef CONFIG_PCI
39 #include <pci.h>
40 #endif
41
42 #include <netdev.h>
43
44 DECLARE_GLOBAL_DATA_PTR;
45
46 void flash__init (void);
47 void ether__init (void);
48 void peripheral_power_enable (void);
49
50 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
51 void show_boot_progress(int progress)
52 {
53 printf("Boot reached stage %d\n", progress);
54 }
55 #endif
56
57 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
58
59 static inline void delay (unsigned long loops)
60 {
61 __asm__ volatile ("1:\n"
62 "subs %0, %1, #1\n"
63 "bne 1b":"=r" (loops):"0" (loops));
64 }
65
66 /*
67 * Miscellaneous platform dependent initialisations
68 */
69
70 int board_init (void)
71 {
72 /* arch number of Integrator Board */
73 gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
74
75 /* adress of boot parameters */
76 gd->bd->bi_boot_params = 0x00000100;
77
78 gd->flags = 0;
79
80 #ifdef CONFIG_CM_REMAP
81 extern void cm_remap(void);
82 cm_remap(); /* remaps writeable memory to 0x00000000 */
83 #endif
84
85 icache_enable ();
86
87 flash__init ();
88 return 0;
89 }
90
91
92 int misc_init_r (void)
93 {
94 #ifdef CONFIG_PCI
95 pci_init();
96 #endif
97 setenv("verify", "n");
98 return (0);
99 }
100
101 /*
102 * Initialize PCI Devices, report devices found.
103 */
104 #ifdef CONFIG_PCI
105
106 #ifndef CONFIG_PCI_PNP
107
108 static struct pci_config_table pci_integrator_config_table[] = {
109 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
110 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
111 PCI_ENET0_MEMADDR,
112 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
113 { }
114 };
115 #endif
116
117 /* V3 access routines */
118 #define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
119 #define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)))
120
121 #define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v))
122 #define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)))
123
124 /* Compute address necessary to access PCI config space for the given */
125 /* bus and device. */
126 #define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({ \
127 unsigned int __address, __devicebit; \
128 unsigned short __mapaddress; \
129 unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */ \
130 \
131 if (__bus == 0) { \
132 /* local bus segment so need a type 0 config cycle */ \
133 /* build the PCI configuration "address" with one-hot in A31-A11 */ \
134 __address = PCI_CONFIG_BASE; \
135 __address |= ((__devfn & 0x07) << 8); \
136 __address |= __offset & 0xFF; \
137 __mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \
138 __devicebit = (1 << (__dev + 11)); \
139 \
140 if ((__devicebit & 0xFF000000) != 0) { \
141 /* high order bits are handled by the MAP register */ \
142 __mapaddress |= (__devicebit >> 16); \
143 } else { \
144 /* low order bits handled directly in the address */ \
145 __address |= __devicebit; \
146 } \
147 } else { /* bus !=0 */ \
148 /* not the local bus segment so need a type 1 config cycle */ \
149 /* A31-A24 are don't care (so clear to 0) */ \
150 __mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \
151 __address = PCI_CONFIG_BASE; \
152 __address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \
153 __address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \
154 __address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number */ \
155 __address |= __offset & 0xFF; /* bits 7..0 = register number */ \
156 } \
157 _V3Write16 (V3_LB_MAP1, __mapaddress); \
158 __address; \
159 })
160
161 /* _V3OpenConfigWindow - open V3 configuration window */
162 #define _V3OpenConfigWindow() { \
163 /* Set up base0 to see all 512Mbytes of memory space (not */ \
164 /* prefetchable), this frees up base1 for re-use by configuration*/ \
165 /* memory */ \
166 \
167 _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
168 0x90 | V3_LB_BASE_M_ENABLE)); \
169 /* Set up base1 to point into configuration space, note that MAP1 */ \
170 /* register is set up by pciMakeConfigAddress(). */ \
171 \
172 _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) | \
173 0x40 | V3_LB_BASE_M_ENABLE)); \
174 }
175
176 /* _V3CloseConfigWindow - close V3 configuration window */
177 #define _V3CloseConfigWindow() { \
178 /* Reassign base1 for use by prefetchable PCI memory */ \
179 _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \
180 | 0x84 | V3_LB_BASE_M_ENABLE)); \
181 _V3Write16 (V3_LB_MAP1, \
182 (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006); \
183 \
184 /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \
185 \
186 _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
187 0x80 | V3_LB_BASE_M_ENABLE)); \
188 }
189
190 static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev,
191 int offset, unsigned char *val)
192 {
193 _V3OpenConfigWindow ();
194 *val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
195 PCI_FUNC (dev),
196 offset);
197 _V3CloseConfigWindow ();
198
199 return 0;
200 }
201
202 static int pci_integrator_read__word (struct pci_controller *hose,
203 pci_dev_t dev, int offset,
204 unsigned short *val)
205 {
206 _V3OpenConfigWindow ();
207 *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
208 PCI_FUNC (dev),
209 offset);
210 _V3CloseConfigWindow ();
211
212 return 0;
213 }
214
215 static int pci_integrator_read_dword (struct pci_controller *hose,
216 pci_dev_t dev, int offset,
217 unsigned int *val)
218 {
219 _V3OpenConfigWindow ();
220 *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
221 PCI_FUNC (dev),
222 offset);
223 *val |= (*(volatile unsigned int *)
224 PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev),
225 (offset + 2))) << 16;
226 _V3CloseConfigWindow ();
227
228 return 0;
229 }
230
231 static int pci_integrator_write_byte (struct pci_controller *hose,
232 pci_dev_t dev, int offset,
233 unsigned char val)
234 {
235 _V3OpenConfigWindow ();
236 *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
237 PCI_FUNC (dev),
238 offset) = val;
239 _V3CloseConfigWindow ();
240
241 return 0;
242 }
243
244 static int pci_integrator_write_word (struct pci_controller *hose,
245 pci_dev_t dev, int offset,
246 unsigned short val)
247 {
248 _V3OpenConfigWindow ();
249 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
250 PCI_FUNC (dev),
251 offset) = val;
252 _V3CloseConfigWindow ();
253
254 return 0;
255 }
256
257 static int pci_integrator_write_dword (struct pci_controller *hose,
258 pci_dev_t dev, int offset,
259 unsigned int val)
260 {
261 _V3OpenConfigWindow ();
262 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
263 PCI_FUNC (dev),
264 offset) = (val & 0xFFFF);
265 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev),
266 PCI_FUNC (dev),
267 (offset + 2)) = ((val >> 16) & 0xFFFF);
268 _V3CloseConfigWindow ();
269
270 return 0;
271 }
272 /******************************
273 * PCI initialisation
274 ******************************/
275
276 struct pci_controller integrator_hose = {
277 #ifndef CONFIG_PCI_PNP
278 config_table: pci_integrator_config_table,
279 #endif
280 };
281
282 void pci_init_board (void)
283 {
284 volatile int i, j;
285 struct pci_controller *hose = &integrator_hose;
286
287 /* setting this register will take the V3 out of reset */
288
289 *(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1;
290
291 /* wait a few usecs to settle the device and the PCI bus */
292
293 for (i = 0; i < 100; i++)
294 j = i + 1;
295
296 /* Now write the Base I/O Address Word to V3_BASE + 0x6C */
297
298 *(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) =
299 (unsigned short) (V3_BASE >> 16);
300
301 do {
302 *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA;
303 *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) =
304 0x55;
305 } while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA
306 || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA +
307 4) != 0x55);
308
309 /* Make sure that V3 register access is not locked, if it is, unlock it */
310
311 if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &
312 V3_SYSTEM_M_LOCK)
313 == V3_SYSTEM_M_LOCK)
314 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F;
315
316 /* Ensure that the slave accesses from PCI are disabled while we */
317 /* setup windows */
318
319 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &=
320 ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN);
321
322 /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */
323
324 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &=
325 ~V3_SYSTEM_M_RST_OUT;
326
327 /* Make all accesses from PCI space retry until we're ready for them */
328
329 *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |=
330 V3_PCI_CFG_M_RETRY_EN;
331
332 /* Set up any V3 PCI Configuration Registers that we absolutely have to */
333 /* LB_CFG controls Local Bus protocol. */
334 /* Enable LocalBus byte strobes for READ accesses too. */
335 /* set bit 7 BE_IMODE and bit 6 BE_OMODE */
336
337 *(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0;
338
339 /* PCI_CMD controls overall PCI operation. */
340 /* Enable PCI bus master. */
341
342 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04;
343
344 /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */
345
346 *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) =
347 (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M |
348 V3_PCI_MAP_M_REG_EN |
349 V3_PCI_MAP_M_ENABLE);
350
351 /* PCI_BASE0 is the PCI address of the start of the window */
352
353 *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) =
354 INTEGRATOR_BOOT_ROM_BASE;
355
356 /* PCI_MAP1 is LOCAL address of the start of the window */
357
358 *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) =
359 (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M |
360 V3_PCI_MAP_M_REG_EN |
361 V3_PCI_MAP_M_ENABLE);
362
363 /* PCI_BASE1 is the PCI address of the start of the window */
364
365 *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) =
366 INTEGRATOR_HDR0_SDRAM_BASE;
367
368 /* Set up the windows from local bus memory into PCI configuration, */
369 /* I/O and Memory. */
370 /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */
371
372 *(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) =
373 ((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE;
374 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0;
375
376 /* PCI Configuration, use LB_BASE1/LB_MAP1. */
377
378 /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */
379 /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */
380 /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */
381
382 *(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) =
383 INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE);
384
385 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) =
386 ((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006;
387
388 /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */
389
390 *(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) =
391 INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE);
392
393 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) =
394 (((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006;
395
396 /* Allow accesses to PCI Configuration space */
397 /* and set up A1, A0 for type 1 config cycles */
398
399 *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) =
400 ((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) &
401 ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) |
402 V3_PCI_CFG_M_AD_LOW0;
403
404 /* now we can allow in PCI MEMORY accesses */
405
406 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) =
407 (*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) |
408 V3_COMMAND_M_MEM_EN;
409
410 /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */
411 /* initialise and lock the V3 system register so that no one else */
412 /* can play with it */
413
414 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
415 (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
416 V3_SYSTEM_M_RST_OUT;
417
418 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) =
419 (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) |
420 V3_SYSTEM_M_LOCK;
421
422 /*
423 * Register the hose
424 */
425 hose->first_busno = 0;
426 hose->last_busno = 0xff;
427
428 /* System memory space */
429 pci_set_region (hose->regions + 0,
430 0x00000000, 0x40000000, 0x01000000,
431 PCI_REGION_MEM | PCI_REGION_MEMORY);
432
433 /* PCI Memory - config space */
434 pci_set_region (hose->regions + 1,
435 0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM);
436
437 /* PCI V3 regs */
438 pci_set_region (hose->regions + 2,
439 0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM);
440
441 /* PCI I/O space */
442 pci_set_region (hose->regions + 3,
443 0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO);
444
445 pci_set_ops (hose,
446 pci_integrator_read_byte,
447 pci_integrator_read__word,
448 pci_integrator_read_dword,
449 pci_integrator_write_byte,
450 pci_integrator_write_word, pci_integrator_write_dword);
451
452 hose->region_count = 4;
453
454 pci_register_hose (hose);
455
456 pciauto_config_init (hose);
457 pciauto_config_device (hose, 0);
458
459 hose->last_busno = pci_hose_scan (hose);
460 }
461 #endif
462
463 /******************************
464 Routine:
465 Description:
466 ******************************/
467 void flash__init (void)
468 {
469 }
470 /*************************************************************
471 Routine:ether__init
472 Description: take the Ethernet controller out of reset and wait
473 for the EEPROM load to complete.
474 *************************************************************/
475 void ether__init (void)
476 {
477 }
478
479 /******************************
480 Routine:
481 Description:
482 ******************************/
483 int dram_init (void)
484 {
485 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
486 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
487
488 #ifdef CONFIG_CM_SPD_DETECT
489 {
490 extern void dram_query(void);
491 unsigned long cm_reg_sdram;
492 unsigned long sdram_shift;
493
494 dram_query(); /* Assembler accesses to CM registers */
495 /* Queries the SPD values */
496
497 /* Obtain the SDRAM size from the CM SDRAM register */
498
499 cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
500 /* Register SDRAM size
501 *
502 * 0xXXXXXXbbb000bb 16 MB
503 * 0xXXXXXXbbb001bb 32 MB
504 * 0xXXXXXXbbb010bb 64 MB
505 * 0xXXXXXXbbb011bb 128 MB
506 * 0xXXXXXXbbb100bb 256 MB
507 *
508 */
509 sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
510 gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
511
512 }
513 #endif /* CM_SPD_DETECT */
514
515 return 0;
516 }
517
518 /* The Integrator/AP timer1 is clocked at 24MHz
519 * can be divided by 16 or 256
520 * and is a 16-bit counter
521 */
522 /* U-Boot expects a 32 bit timer running at CONFIG_SYS_HZ*/
523 static ulong timestamp; /* U-Boot ticks since startup */
524 static ulong total_count = 0; /* Total timer count */
525 static ulong lastdec; /* Timer reading at last call */
526 static ulong div_clock = 256; /* Divisor applied to the timer clock */
527 static ulong div_timer = 1; /* Divisor to convert timer reading
528 * change to U-Boot ticks
529 */
530 /* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
531
532 #define TIMER_LOAD_VAL 0x0000FFFFL
533 #define READ_TIMER ((*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) & 0x0000FFFFL)
534
535 /* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
536 * - unless otherwise stated
537 */
538
539 /* starts a counter
540 * - the Integrator/AP timer issues an interrupt
541 * each time it reaches zero
542 */
543 int interrupt_init (void)
544 {
545 /* Load timer with initial value */
546 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
547 /* Set timer to be
548 * enabled 1
549 * free-running 0
550 * XX 00
551 * divider 256 10
552 * XX 00
553 */
554 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
555 total_count = 0;
556 /* init the timestamp and lastdec value */
557 reset_timer_masked();
558
559 div_timer = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
560 div_timer /= div_clock;
561
562 return (0);
563 }
564
565 /*
566 * timer without interrupts
567 */
568 void reset_timer (void)
569 {
570 reset_timer_masked ();
571 }
572
573 ulong get_timer (ulong base_ticks)
574 {
575 return get_timer_masked () - base_ticks;
576 }
577
578 void set_timer (ulong ticks)
579 {
580 timestamp = ticks;
581 total_count = ticks * div_timer;
582 reset_timer_masked();
583 }
584
585 /* delay x useconds */
586 void udelay (unsigned long usec)
587 {
588 ulong tmo, tmp;
589
590 /* Convert to U-Boot ticks */
591 tmo = usec * CONFIG_SYS_HZ;
592 tmo /= (1000000L);
593
594 tmp = get_timer_masked(); /* get current timestamp */
595 tmo += tmp; /* wake up timestamp */
596
597 while (get_timer_masked () < tmo) { /* loop till event */
598 /*NOP*/;
599 }
600 }
601
602 void reset_timer_masked (void)
603 {
604 /* reset time */
605 lastdec = READ_TIMER; /* capture current decrementer value */
606 timestamp = 0; /* start "advancing" time stamp from 0 */
607 }
608
609 /* converts the timer reading to U-Boot ticks */
610 /* the timestamp is the number of ticks since reset */
611 /* This routine does not detect wraps unless called regularly
612 ASSUMES a call at least every 16 seconds to detect every reload */
613 ulong get_timer_masked (void)
614 {
615 ulong now = READ_TIMER; /* current count */
616
617 if (now > lastdec) {
618 /* Must have wrapped */
619 total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
620 } else {
621 total_count += lastdec - now;
622 }
623 lastdec = now;
624 timestamp = total_count/div_timer;
625
626 return timestamp;
627 }
628
629 /* waits specified delay value and resets timestamp */
630 void udelay_masked (unsigned long usec)
631 {
632 udelay(usec);
633 }
634
635 /*
636 * This function is derived from PowerPC code (read timebase as long long).
637 * On ARM it just returns the timer value.
638 */
639 unsigned long long get_ticks(void)
640 {
641 return get_timer(0);
642 }
643
644 /*
645 * Return the timebase clock frequency
646 * i.e. how often the timer decrements
647 */
648 ulong get_tbclk (void)
649 {
650 return CONFIG_SYS_HZ_CLOCK/div_clock;
651 }
652
653 int board_eth_init(bd_t *bis)
654 {
655 return pci_eth_init(bis);
656 }
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