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git.ipfire.org Git - people/ms/u-boot.git/blob - board/ip860/ip860.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /* ------------------------------------------------------------------------- */
30 static long int dram_size (long int, long int *, long int);
31 unsigned long ip860_get_dram_size(void);
32 unsigned long ip860_get_clk_freq (void);
33 /* ------------------------------------------------------------------------- */
35 #define _NOT_USED_ 0xFFFFFFFF
37 const uint sdram_table
[] = {
39 * Single Read. (Offset 0 in UPMA RAM)
41 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
42 0x1ff77c47, /* last */
44 * SDRAM Initialization (offset 5 in UPMA RAM)
46 * This is no UPM entry point. The following definition uses
47 * the remaining space to establish an initialization
48 * sequence, which is executed by a RUN command.
51 0x1ff77c34, 0xefeabc34, 0x1fb57c35, /* last */
53 * Burst Read. (Offset 8 in UPMA RAM)
55 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
56 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
57 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
58 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
60 * Single Write. (Offset 18 in UPMA RAM)
62 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
63 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
65 * Burst Write. (Offset 20 in UPMA RAM)
67 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
68 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */
70 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
71 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
73 * Refresh (Offset 30 in UPMA RAM)
75 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
76 0xfffffc84, 0xfffffc07, /* last */
77 _NOT_USED_
, _NOT_USED_
,
78 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
80 * Exception. (Offset 3c in UPMA RAM)
82 0x7ffffc07, /* last */
83 _NOT_USED_
, _NOT_USED_
, _NOT_USED_
,
87 /* ------------------------------------------------------------------------- */
88 int board_pre_init(void)
90 volatile immap_t
*immap
= (immap_t
*)CFG_IMMR
;
91 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
93 /* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */
94 memctl
->memc_or4
= CFG_OR4
;
95 memctl
->memc_br4
= CFG_BR4
;
101 /* ------------------------------------------------------------------------- */
104 * Check Board Identity:
106 * Test ID string (IP860...)
109 int checkboard (void)
111 unsigned char *s
, *e
;
112 unsigned char buf
[64];
117 i
= getenv_r ("serial#", buf
, sizeof (buf
));
118 s
= (i
> 0) ? buf
: NULL
;
120 if (!s
|| strncmp (s
, "IP860", 5)) {
121 puts ("### No HW ID - assuming IP860");
123 for (e
= s
; *e
; ++e
) {
138 /* ------------------------------------------------------------------------- */
140 long int initdram (int board_type
)
142 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
143 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
147 upmconfig (UPMA
, (uint
*) sdram_table
,
148 sizeof (sdram_table
) / sizeof (uint
));
151 * Preliminary prescaler for refresh
153 if (ip860_get_clk_freq() == 50000000)
155 memctl
->memc_mptpr
= 0x0400;
156 refresh_val
= 0xC3000000;
160 memctl
->memc_mptpr
= 0x0200;
161 refresh_val
= 0x9C000000;
165 memctl
->memc_mar
= 0x00000088;
168 * Map controller banks 2 to the SDRAM address
170 memctl
->memc_or2
= CFG_OR2
;
171 memctl
->memc_br2
= CFG_BR2
;
173 /* IP860 boards have only one bank SDRAM */
178 /* perform SDRAM initializsation sequence */
180 memctl
->memc_mamr
= 0x00804114 | refresh_val
;
181 memctl
->memc_mcr
= 0x80004105; /* run precharge pattern from loc 5 */
183 memctl
->memc_mamr
= 0x00804118 | refresh_val
;
184 memctl
->memc_mcr
= 0x80004130; /* run refresh pattern 8 times */
190 * Check SDRAM Memory Size
192 if (ip860_get_dram_size() == 16)
193 size
= dram_size (refresh_val
| 0x00804114, (ulong
*)SDRAM_BASE
, SDRAM_MAX_SIZE
);
195 size
= dram_size (refresh_val
| 0x00906114, (ulong
*)SDRAM_BASE
, SDRAM_MAX_SIZE
);
199 memctl
->memc_or2
= ((-size
) & 0xFFFF0000) | SDRAM_TIMING
;
200 memctl
->memc_br2
= (CFG_SDRAM_BASE
& BR_BA_MSK
) | BR_MS_UPMA
| BR_V
;
205 * Also, map other memory to correct position
208 #if (defined(CFG_OR1) && defined(CFG_BR1_PRELIM))
209 memctl
->memc_or1
= CFG_OR1
;
210 memctl
->memc_br1
= CFG_BR1
;
213 #if defined(CFG_OR3) && defined(CFG_BR3)
214 memctl
->memc_or3
= CFG_OR3
;
215 memctl
->memc_br3
= CFG_BR3
;
218 #if defined(CFG_OR4) && defined(CFG_BR4)
219 memctl
->memc_or4
= CFG_OR4
;
220 memctl
->memc_br4
= CFG_BR4
;
223 #if defined(CFG_OR5) && defined(CFG_BR5)
224 memctl
->memc_or5
= CFG_OR5
;
225 memctl
->memc_br5
= CFG_BR5
;
228 #if defined(CFG_OR6) && defined(CFG_BR6)
229 memctl
->memc_or6
= CFG_OR6
;
230 memctl
->memc_br6
= CFG_BR6
;
233 #if defined(CFG_OR7) && defined(CFG_BR7)
234 memctl
->memc_or7
= CFG_OR7
;
235 memctl
->memc_br7
= CFG_BR7
;
241 /* ------------------------------------------------------------------------- */
244 * Check memory range for valid RAM. A simple memory test determines
245 * the actually available RAM size between addresses `base' and
246 * `base + maxsize'. Some (not all) hardware errors are detected:
247 * - short between address lines
248 * - short between data lines
251 static long int dram_size (long int mamr_value
, long int *base
,
254 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
255 volatile memctl8xx_t
*memctl
= &immap
->im_memctl
;
256 volatile long int *addr
;
258 ulong save
[32]; /* to make test non-destructive */
261 memctl
->memc_mamr
= mamr_value
;
263 for (cnt
= maxsize
/ sizeof (long); cnt
> 0; cnt
>>= 1) {
264 addr
= base
+ cnt
; /* pointer arith! */
270 /* write 0 to base address */
275 /* check at base address */
276 if ((val
= *addr
) != 0) {
281 for (cnt
= 1; cnt
<= maxsize
/ sizeof (long); cnt
<<= 1) {
282 addr
= base
+ cnt
; /* pointer arith! */
288 return (cnt
* sizeof (long));
294 /* ------------------------------------------------------------------------- */
296 void reset_phy (void)
298 volatile immap_t
*immr
= (immap_t
*) CFG_IMMR
;
299 ulong mask
= PB_ENET_RESET
| PB_ENET_JABD
;
302 /* Make sure PHY is not in low-power mode */
303 immr
->im_cpm
.cp_pbpar
&= ~(mask
); /* GPIO */
304 immr
->im_cpm
.cp_pbodr
&= ~(mask
); /* active output */
306 /* Set JABD low (no JABber Disable),
307 * and RESET high (Reset PHY)
309 reg
= immr
->im_cpm
.cp_pbdat
;
310 reg
= (reg
& ~PB_ENET_JABD
) | PB_ENET_RESET
;
311 immr
->im_cpm
.cp_pbdat
= reg
;
313 /* now drive outputs */
314 immr
->im_cpm
.cp_pbdir
|= mask
; /* output */
317 * Release RESET signal
319 immr
->im_cpm
.cp_pbdat
&= ~(PB_ENET_RESET
);
323 /* ------------------------------------------------------------------------- */
325 unsigned long ip860_get_clk_freq(void)
327 volatile ip860_bcsr_t
*bcsr
= (ip860_bcsr_t
*)BCSR_BASE
;
331 if ((bcsr
->bd_status
& 0x80) == 0x80) /* bd_rev valid ? */
332 sysclk
= (bcsr
->bd_rev
& 0x18) >> 3;
356 /* ------------------------------------------------------------------------- */
358 unsigned long ip860_get_dram_size(void)
360 volatile ip860_bcsr_t
*bcsr
= (ip860_bcsr_t
*)BCSR_BASE
;
364 if ((bcsr
->bd_status
& 0x80) == 0x80) /* bd_rev valid ? */
365 dram_size
= (bcsr
->bd_rev
& 0xE0) >> 5;
367 dram_size
= 0x00; /* default is 16 MB */
388 /* ------------------------------------------------------------------------- */