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git.ipfire.org Git - thirdparty/u-boot.git/blob - board/ipek01/ipek01.c
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
12 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
14 * SPDX-License-Identifier: GPL-2.0+
25 #include <asm/processor.h>
28 #ifdef CONFIG_OF_LIBFDT
29 #include <fdt_support.h>
30 #endif /* CONFIG_OF_LIBFDT */
33 #ifdef CONFIG_MPC5200_DDR
34 /* Settings for XLB = 132 MHz */
35 #define SDRAM_MODE 0x018D0000
36 #define SDRAM_EMODE 0x40090000
37 #define SDRAM_CONTROL 0x714f0f00
38 #define SDRAM_CONFIG1 0x73722930
39 #define SDRAM_CONFIG2 0x47770000
40 #define SDRAM_TAPDELAY 0x10000000
42 #error SDRAM is not supported on this board
45 DECLARE_GLOBAL_DATA_PTR
;
47 static void sdram_start (int hi_addr
)
49 struct mpc5xxx_sdram
*sdram
= (struct mpc5xxx_sdram
*)MPC5XXX_SDRAM
;
50 long hi_addr_bit
= hi_addr
? 0x01000000 : 0;
52 /* unlock mode register */
53 out_be32 (&sdram
->ctrl
, SDRAM_CONTROL
| 0x80000000 | hi_addr_bit
);
55 /* precharge all banks */
56 out_be32 (&sdram
->ctrl
, SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
);
58 /* set mode register: extended mode */
59 out_be32 (&sdram
->mode
, SDRAM_EMODE
);
61 /* set mode register: reset DLL */
62 out_be32 (&sdram
->mode
, SDRAM_MODE
| 0x04000000);
64 /* precharge all banks */
65 out_be32 (&sdram
->ctrl
, SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
);
68 out_be32 (&sdram
->ctrl
, SDRAM_CONTROL
| 0x80000004 | hi_addr_bit
);
70 /* set mode register */
71 out_be32 (&sdram
->mode
, SDRAM_MODE
);
73 /* normal operation */
74 out_be32 (&sdram
->ctrl
, SDRAM_CONTROL
| hi_addr_bit
);
78 * ATTENTION: Although partially referenced dram_init does NOT make real
79 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
80 * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
85 struct mpc5xxx_mmap_ctl
*mmap_ctl
=
86 (struct mpc5xxx_mmap_ctl
*)CONFIG_SYS_MBAR
;
87 struct mpc5xxx_sdram
*sdram
= (struct mpc5xxx_sdram
*)MPC5XXX_SDRAM
;
88 struct mpc5xxx_cdm
*cdm
= (struct mpc5xxx_cdm
*)MPC5XXX_CDM
;
93 /* setup SDRAM chip selects */
94 out_be32 (&mmap_ctl
->sdram0
, 0x0000001e); /* 2G at 0x0 */
95 out_be32 (&mmap_ctl
->sdram1
, 0x00000000); /* disabled */
97 /* setup config registers */
98 out_be32 (&sdram
->config1
, SDRAM_CONFIG1
);
99 out_be32 (&sdram
->config2
, SDRAM_CONFIG2
);
102 out_be32 (&cdm
->porcfg
, SDRAM_TAPDELAY
);
104 /* find RAM size using SDRAM CS0 only */
106 test1
= get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE
, 0x80000000);
108 test2
= get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE
, 0x80000000);
116 /* memory smaller than 1MB is impossible */
117 if (dramsize
< (1 << 20))
120 /* set SDRAM CS0 size according to the amount of RAM found */
122 out_be32 (&mmap_ctl
->sdram0
,
123 0x13 + __builtin_ffs (dramsize
>> 20) - 1);
125 out_be32 (&mmap_ctl
->sdram1
, 0); /* disabled */
128 * On MPC5200B we need to set the special configuration delay in the
129 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
130 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
132 * "The SDelay should be written to a value of 0x00000004. It is
133 * required to account for changes caused by normal wafer processing
136 out_be32 (&sdram
->sdelay
, 0x04);
138 gd
->ram_size
= dramsize
+ dramsize2
;
143 int checkboard (void)
145 puts ("Board: IPEK01 \n");
149 void flash_preinit (void)
151 struct mpc5xxx_lpb
*lpb
= (struct mpc5xxx_lpb
*)MPC5XXX_LPB
;
154 * Now, when we are in RAM, enable flash write
155 * access for detection process.
156 * Note that CS_BOOT cannot be cleared when
157 * executing in flash.
159 clrbits_be32 (&lpb
->cs0_cfg
, 0x1); /* clear RO */
162 void flash_afterinit (ulong start
, ulong size
)
164 struct mpc5xxx_mmap_ctl
*mmap_ctl
=
165 (struct mpc5xxx_mmap_ctl
*)CONFIG_SYS_MBAR
;
167 #if defined(CONFIG_BOOT_ROM)
169 out_be32 (&mmap_ctl
->cs1_start
, START_REG (start
));
170 out_be32 (&mmap_ctl
->cs1_stop
, STOP_REG (start
, size
));
173 out_be32 (&mmap_ctl
->boot_start
, START_REG (start
));
174 out_be32 (&mmap_ctl
->cs0_start
, START_REG (start
));
175 out_be32 (&mmap_ctl
->boot_stop
, STOP_REG (start
, size
));
176 out_be32 (&mmap_ctl
->cs0_stop
, STOP_REG (start
, size
));
180 extern flash_info_t flash_info
[]; /* info for FLASH chips */
182 int misc_init_r (void)
184 /* adjust flash start */
185 gd
->bd
->bi_flashstart
= flash_info
[0].start
[0];
190 static struct pci_controller hose
;
192 extern void pci_mpc5xxx_init (struct pci_controller
*);
194 void pci_init_board (void)
196 pci_mpc5xxx_init (&hose
);
200 #ifdef CONFIG_OF_BOARD_SETUP
201 int ft_board_setup(void *blob
, bd_t
*bd
)
203 ft_cpu_setup (blob
, bd
);
204 fdt_fixup_memory (blob
, (u64
) bd
->bi_memstart
, (u64
) bd
->bi_memsize
);
208 #endif /* CONFIG_OF_BOARD_SETUP */
210 int board_eth_init(bd_t
*bis
)
212 cpu_eth_init(bis
); /* Built in FEC comes first */
213 return pci_eth_init(bis
);
217 extern GraphicDevice mb862xx
;
219 static const gdc_regs init_regs
[] = {
220 {0x0100, 0x00000900},
221 {0x0020, 0x80190257},
222 {0x0024, 0x00000000},
223 {0x0028, 0x00000000},
224 {0x002c, 0x00000000},
225 {0x0110, 0x00000000},
226 {0x0114, 0x00000000},
227 {0x0118, 0x02570320},
228 {0x0004, 0x041f0000},
229 {0x0008, 0x031f031f},
230 {0x000c, 0x067f0347},
231 {0x0010, 0x02780000},
232 {0x0014, 0x0257025c},
233 {0x0018, 0x00000000},
234 {0x001c, 0x02570320},
235 {0x0100, 0x80010900},
239 const gdc_regs
*board_get_regs (void)
244 /* Returns Lime base address */
245 unsigned int board_video_init (void)
247 if (mb862xx_probe (CONFIG_SYS_LIME_BASE
) != MB862XX_TYPE_LIME
)
250 mb862xx
.winSizeX
= 800;
251 mb862xx
.winSizeY
= 600;
252 mb862xx
.gdfIndex
= GDF_15BIT_555RGB
;
253 mb862xx
.gdfBytesPP
= 2;
255 return CONFIG_SYS_LIME_BASE
;
258 #if defined(CONFIG_CONSOLE_EXTRA_INFO)
260 * Return text to be printed besides the logo.
262 void video_get_info_str (int line_number
, char *info
)
264 if (line_number
== 1)
265 strcpy (info
, " Board: IPEK01");
270 #endif /* CONFIG_VIDEO */