board/isee/igep0020/igep0020.c

   1 /*
   2  * (C) Copyright 2010
   3  * ISEE 2007 SL, <www.iseebcn.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #include <common.h>
  24 #include <netdev.h>
  25 #include <twl4030.h>
  26 #include <asm/io.h>
  27 #include <asm/gpio.h>
  28 #include <asm/arch/mem.h>
  29 #include <asm/arch/mmc_host_def.h>
  30 #include <asm/arch/mux.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <asm/arch/omap_gpmc.h>
  33 #include <asm/mach-types.h>
  34 #include "igep0020.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 /* GPMC definitions for LAN9221 chips */
  39 static const u32 gpmc_lan_config[] = {
  40     NET_LAN9221_GPMC_CONFIG1,
  41     NET_LAN9221_GPMC_CONFIG2,
  42     NET_LAN9221_GPMC_CONFIG3,
  43     NET_LAN9221_GPMC_CONFIG4,
  44     NET_LAN9221_GPMC_CONFIG5,
  45     NET_LAN9221_GPMC_CONFIG6,
  46 };
  47
  48 /*
  49  * Routine: board_init
  50  * Description: Early hardware init.
  51  */
  52 int board_init(void)
  53 {
  54         gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  55         /* board id for Linux */
  56         gd->bd->bi_arch_number = MACH_TYPE_IGEP0020;
  57         /* boot param addr */
  58         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  59
  60         return 0;
  61 }
  62
  63 /*
  64  * Routine: setup_net_chip
  65  * Description: Setting up the configuration GPMC registers specific to the
  66  *              Ethernet hardware.
  67  */
  68 #if defined(CONFIG_CMD_NET)
  69 static void setup_net_chip(void)
  70 {
  71         struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
  72
  73         enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
  74                         GPMC_SIZE_16M);
  75
  76         /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
  77         writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
  78         /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
  79         writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
  80         /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
  81         writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
  82                 &ctrl_base->gpmc_nadv_ale);
  83
  84         /* Make GPIO 64 as output pin and send a magic pulse through it */
  85         if (!gpio_request(64, "")) {
  86                 gpio_direction_output(64, 0);
  87                 gpio_set_value(64, 1);
  88                 udelay(1);
  89                 gpio_set_value(64, 0);
  90                 udelay(1);
  91                 gpio_set_value(64, 1);
  92         }
  93 }
  94 #endif
  95
  96 #ifdef CONFIG_GENERIC_MMC
  97 int board_mmc_init(bd_t *bis)
  98 {
  99         omap_mmc_init(0);
 100         return 0;
 101 }
 102 #endif
 103
 104 /*
 105  * Routine: misc_init_r
 106  * Description: Configure board specific parts
 107  */
 108 int misc_init_r(void)
 109 {
 110         twl4030_power_init();
 111
 112 #if defined(CONFIG_CMD_NET)
 113         setup_net_chip();
 114 #endif
 115
 116         dieid_num_r();
 117
 118         return 0;
 119 }
 120
 121 /*
 122  * Routine: set_muxconf_regs
 123  * Description: Setting up the configuration Mux registers specific to the
 124  *              hardware. Many pins need to be moved from protect to primary
 125  *              mode.
 126  */
 127 void set_muxconf_regs(void)
 128 {
 129         MUX_DEFAULT();
 130 }
 131
 132 int board_eth_init(bd_t *bis)
 133 {
 134         int rc = 0;
 135 #ifdef CONFIG_SMC911X
 136         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 137 #endif
 138         return rc;
 139 }