board/isee/igep00x0/igep00x0.c

   1 /*
   2  * (C) Copyright 2010
   3  * ISEE 2007 SL, <www.iseebcn.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <status_led.h>
   9 #include <dm.h>
  10 #include <ns16550.h>
  11 #include <twl4030.h>
  12 #include <netdev.h>
  13 #include <asm/gpio.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/mem.h>
  16 #include <asm/arch/mmc_host_def.h>
  17 #include <asm/arch/mux.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/mach-types.h>
  20 #include "igep00x0.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #if defined(CONFIG_CMD_NET)
  25 /* GPMC definitions for LAN9221 chips */
  26 static const u32 gpmc_lan_config[] = {
  27         NET_LAN9221_GPMC_CONFIG1,
  28         NET_LAN9221_GPMC_CONFIG2,
  29         NET_LAN9221_GPMC_CONFIG3,
  30         NET_LAN9221_GPMC_CONFIG4,
  31         NET_LAN9221_GPMC_CONFIG5,
  32         NET_LAN9221_GPMC_CONFIG6,
  33 };
  34 #endif
  35
  36 static const struct ns16550_platdata igep_serial = {
  37         OMAP34XX_UART3,
  38         2,
  39         V_NS16550_CLK
  40 };
  41
  42 U_BOOT_DEVICE(igep_uart) = {
  43         "serial_omap",
  44         &igep_serial
  45 };
  46
  47 /*
  48  * Routine: board_init
  49  * Description: Early hardware init.
  50  */
  51 int board_init(void)
  52 {
  53         gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  54         /* boot param addr */
  55         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  56
  57 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
  58         status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
  59 #endif
  60
  61         return 0;
  62 }
  63
  64 #ifdef CONFIG_SPL_BUILD
  65 /*
  66  * Routine: omap_rev_string
  67  * Description: For SPL builds output board rev
  68  */
  69 void omap_rev_string(void)
  70 {
  71 }
  72
  73 /*
  74  * Routine: get_board_mem_timings
  75  * Description: If we use SPL then there is no x-loader nor config header
  76  * so we have to setup the DDR timings ourself on both banks.
  77  */
  78 void get_board_mem_timings(struct board_sdrc_timings *timings)
  79 {
  80         timings->mr = MICRON_V_MR_165;
  81 #ifdef CONFIG_BOOT_NAND
  82         timings->mcfg = MICRON_V_MCFG_200(256 << 20);
  83         timings->ctrla = MICRON_V_ACTIMA_200;
  84         timings->ctrlb = MICRON_V_ACTIMB_200;
  85         timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  86 #else
  87         if (get_cpu_family() == CPU_OMAP34XX) {
  88                 timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
  89                 timings->ctrla = NUMONYX_V_ACTIMA_165;
  90                 timings->ctrlb = NUMONYX_V_ACTIMB_165;
  91                 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  92
  93         } else {
  94                 timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
  95                 timings->ctrla = NUMONYX_V_ACTIMA_200;
  96                 timings->ctrlb = NUMONYX_V_ACTIMB_200;
  97                 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  98         }
  99 #endif
 100 }
 101 #endif
 102
 103 #if defined(CONFIG_CMD_NET)
 104 /*
 105  * Routine: setup_net_chip
 106  * Description: Setting up the configuration GPMC registers specific to the
 107  *              Ethernet hardware.
 108  */
 109 static void setup_net_chip(void)
 110 {
 111         struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 112
 113         enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
 114                         GPMC_SIZE_16M);
 115
 116         /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 117         writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
 118         /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
 119         writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
 120         /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
 121         writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
 122                 &ctrl_base->gpmc_nadv_ale);
 123
 124         /* Make GPIO 64 as output pin and send a magic pulse through it */
 125         if (!gpio_request(64, "")) {
 126                 gpio_direction_output(64, 0);
 127                 gpio_set_value(64, 1);
 128                 udelay(1);
 129                 gpio_set_value(64, 0);
 130                 udelay(1);
 131                 gpio_set_value(64, 1);
 132         }
 133 }
 134 #else
 135 static inline void setup_net_chip(void) {}
 136 #endif
 137
 138 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 139 int board_mmc_init(bd_t *bis)
 140 {
 141         return omap_mmc_init(0, 0, 0, -1, -1);
 142 }
 143 #endif
 144
 145 #if defined(CONFIG_GENERIC_MMC)
 146 void board_mmc_power_init(void)
 147 {
 148         twl4030_power_mmc_init(0);
 149 }
 150 #endif
 151
 152 void set_fdt(void)
 153 {
 154         switch (gd->bd->bi_arch_number) {
 155         case MACH_TYPE_IGEP0020:
 156                 setenv("fdtfile", "omap3-igep0020.dtb");
 157                 break;
 158         case MACH_TYPE_IGEP0030:
 159                 setenv("fdtfile", "omap3-igep0030.dtb");
 160                 break;
 161         }
 162 }
 163
 164 /*
 165  * Routine: misc_init_r
 166  * Description: Configure board specific parts
 167  */
 168 int misc_init_r(void)
 169 {
 170         twl4030_power_init();
 171
 172         setup_net_chip();
 173
 174         omap_die_id_display();
 175
 176         set_fdt();
 177
 178         return 0;
 179 }
 180
 181 /*
 182  * Routine: set_muxconf_regs
 183  * Description: Setting up the configuration Mux registers specific to the
 184  *              hardware. Many pins need to be moved from protect to primary
 185  *              mode.
 186  */
 187 void set_muxconf_regs(void)
 188 {
 189         MUX_DEFAULT();
 190
 191 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
 192         MUX_IGEP0020();
 193 #endif
 194
 195 #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
 196         MUX_IGEP0030();
 197 #endif
 198 }
 199
 200 #if defined(CONFIG_CMD_NET)
 201 int board_eth_init(bd_t *bis)
 202 {
 203         int rc = 0;
 204 #ifdef CONFIG_SMC911X
 205         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 206 #endif
 207         return rc;
 208 }
 209 #endif