board/jse/init.S

   1 /*------------------------------------------------------------------------+ */
   2 /* */
   3 /*       This source code has been made available to you by IBM on an AS-IS */
   4 /*       basis.  Anyone receiving this source is licensed under IBM */
   5 /*       copyrights to use it in any way he or she deems fit, including */
   6 /*       copying it, modifying it, compiling it, and redistributing it either */
   7 /*       with or without modifications.  No license under IBM patents or */
   8 /*       patent applications is to be implied by the copyright license. */
   9 /* */
  10 /*       Any user of this software should understand that IBM cannot provide */
  11 /*       technical support for this software and will not be responsible for */
  12 /*       any consequences resulting from the use of this software. */
  13 /* */
  14 /*       Any person who transfers this source code or any derivative work */
  15 /*       must include the IBM copyright notice, this paragraph, and the */
  16 /*       preceding two paragraphs in the transferred software. */
  17 /* */
  18 /*       COPYRIGHT   I B M   CORPORATION 1995 */
  19 /*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
  20 /*------------------------------------------------------------------------- */
  21
  22 /*------------------------------------------------------------------------- */
  23 /* Function:     ext_bus_cntlr_init */
  24 /* Description:  Initializes the External Bus Controller for the external */
  25 /*              peripherals. IMPORTANT: For pass1 this code must run from */
  26 /*              cache since you can not reliably change a peripheral banks */
  27 /*              timing register (pbxap) while running code from that bank. */
  28 /*              For ex., since we are running from ROM on bank 0, we can NOT */
  29 /*              execute the code that modifies bank 0 timings from ROM, so */
  30 /*              we run it from cache. */
  31 /*                                    */
  32 /*                                    */
  33 /* The layout for the PEI JSE board:  */
  34 /*      Bank 0 - Flash and SRAM       */
  35 /*      Bank 1 - SystemACE            */
  36 /*      Bank 2 - not used             */
  37 /*      Bank 3 - not used             */
  38 /*      Bank 4 - not used             */
  39 /*      Bank 5 - not used             */
  40 /*      Bank 6 - not used             */
  41 /*      Bank 7 - not used             */
  42 /*------------------------------------------------------------------------- */
  43 #include <ppc4xx.h>
  44
  45 #include <ppc_asm.tmpl>
  46 #include <ppc_defs.h>
  47
  48 #include <asm/cache.h>
  49 #include <asm/mmu.h>
  50
  51 #define cpc0_cr0 0xB1
  52
  53         .globl  ext_bus_cntlr_init
  54 ext_bus_cntlr_init:
  55         mflr    r4                      /* save link register */
  56         bl      ..getAddr
  57 ..getAddr:
  58         mflr    r3                      /* get address of ..getAddr */
  59         mtlr    r4                      /* restore link register */
  60         addi    r4,0,14                 /* set ctr to 10; used to prefetch */
  61         mtctr   r4                      /* 10 cache lines to fit this function */
  62                                         /* in cache (gives us 8x10=80 instrctns) */
  63 ..ebcloop:
  64         icbt    r0,r3                   /* prefetch cache line for addr in r3 */
  65         addi    r3,r3,32                /* move to next cache line */
  66         bdnz    ..ebcloop               /* continue for 10 cache lines */
  67
  68         /*----------------------------------------------------------------- */
  69         /* Delay to ensure all accesses to ROM are complete before changing */
  70         /* bank 0 timings. 200usec should be enough. */
  71         /*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
  72         /*----------------------------------------------------------------- */
  73         addis   r3,0,0x0
  74         ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
  75         mtctr   r3
  76 ..spinlp:
  77         bdnz    ..spinlp                /* spin loop */
  78
  79         /*----------------------------------------------------------------- */
  80         /* Memory Bank 0 (Flash) initialization */
  81         /*----------------------------------------------------------------- */
  82
  83         addi    r4,0,pb0ap
  84         mtdcr   ebccfga,r4
  85         addis   r4,0,0x9B01
  86         ori     r4,r4,0x5480
  87         mtdcr   ebccfgd,r4
  88
  89         addi    r4,0,pb0cr
  90         mtdcr   ebccfga,r4
  91         addis   r4,0,0xFFF1           /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
  92         ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
  93         mtdcr   ebccfgd,r4
  94
  95         blr
  96
  97
  98 /*----------------------------------------------------------------------- */
  99 /* Function:     sdram_init                                               */
 100 /* Description:  This function is called by cpu/ppc4xx/start.S code       */
 101 /*               to get the SDRAM initialized.                            */
 102 /*----------------------------------------------------------------------- */
 103         .globl  sdram_init
 104 sdram_init:
 105         blr