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git.ipfire.org Git - people/ms/u-boot.git/blob - board/jupiter/jupiter.c
ea24eaa5c01c1fadc1cc5c5e0c44fee95827b474
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/processor.h>
19 /* Settings Icecube */
20 #define SDRAM_MODE 0x00CD0000
21 #define SDRAM_CONTROL 0x504F0000
22 #define SDRAM_CONFIG1 0xD2322800
23 #define SDRAM_CONFIG2 0x8AD70000
25 /*Settings Jupiter UB 1.0.0 */
26 #define SDRAM_MODE 0x008D0000
27 #define SDRAM_CONTROL 0xD04F0000
28 #define SDRAM_CONFIG1 0xf7277f00
29 #define SDRAM_CONFIG2 0x88b70004
32 DECLARE_GLOBAL_DATA_PTR
;
34 #ifndef CONFIG_SYS_RAMBOOT
35 static void sdram_start (int hi_addr
)
37 long hi_addr_bit
= hi_addr
? 0x01000000 : 0;
39 /* unlock mode register */
40 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000000 | hi_addr_bit
;
41 __asm__
volatile ("sync");
43 /* precharge all banks */
44 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
;
45 __asm__
volatile ("sync");
48 /* set mode register: extended mode */
49 *(vu_long
*)MPC5XXX_SDRAM_MODE
= SDRAM_EMODE
;
50 __asm__
volatile ("sync");
52 /* set mode register: reset DLL */
53 *(vu_long
*)MPC5XXX_SDRAM_MODE
= SDRAM_MODE
| 0x04000000;
54 __asm__
volatile ("sync");
57 /* precharge all banks */
58 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
;
59 __asm__
volatile ("sync");
62 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000004 | hi_addr_bit
;
63 __asm__
volatile ("sync");
65 /* set mode register */
66 *(vu_long
*)MPC5XXX_SDRAM_MODE
= SDRAM_MODE
;
67 __asm__
volatile ("sync");
69 /* normal operation */
70 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| hi_addr_bit
;
71 __asm__
volatile ("sync");
76 * ATTENTION: Although partially referenced dram_init does NOT make real use
77 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
78 * is something else than 0x00000000.
87 #ifndef CONFIG_SYS_RAMBOOT
90 /* setup SDRAM chip selects */
91 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0x0000001e;/* 2G at 0x0 */
92 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= 0x80000000;/* disabled */
93 __asm__
volatile ("sync");
95 /* setup config registers */
96 *(vu_long
*)MPC5XXX_SDRAM_CONFIG1
= SDRAM_CONFIG1
;
97 *(vu_long
*)MPC5XXX_SDRAM_CONFIG2
= SDRAM_CONFIG2
;
98 __asm__
volatile ("sync");
102 *(vu_long
*)MPC5XXX_CDM_PORCFG
= SDRAM_TAPDELAY
;
103 __asm__
volatile ("sync");
106 /* find RAM size using SDRAM CS0 only */
108 test1
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x80000000);
110 test2
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x80000000);
118 /* memory smaller than 1MB is impossible */
119 if (dramsize
< (1 << 20)) {
123 /* set SDRAM CS0 size according to the amount of RAM found */
125 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0x13 + __builtin_ffs(dramsize
>> 20) - 1;
127 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0; /* disabled */
130 /* let SDRAM CS1 start right after CS0 */
131 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
+ 0x0000001e;/* 2G */
133 /* find RAM size using SDRAM CS1 only */
136 test2
= test1
= get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE
+ dramsize
), 0x80000000);
139 test2
= get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE
+ dramsize
), 0x80000000);
148 /* memory smaller than 1MB is impossible */
149 if (dramsize2
< (1 << 20)) {
153 /* set SDRAM CS1 size according to the amount of RAM found */
155 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
156 | (0x13 + __builtin_ffs(dramsize2
>> 20) - 1);
158 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
; /* disabled */
161 #else /* CONFIG_SYS_RAMBOOT */
163 /* retrieve size of memory connected to SDRAM CS0 */
164 dramsize
= *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
& 0xFF;
165 if (dramsize
>= 0x13) {
166 dramsize
= (1 << (dramsize
- 0x13)) << 20;
171 /* retrieve size of memory connected to SDRAM CS1 */
172 dramsize2
= *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
& 0xFF;
173 if (dramsize2
>= 0x13) {
174 dramsize2
= (1 << (dramsize2
- 0x13)) << 20;
179 #endif /* CONFIG_SYS_RAMBOOT */
182 * On MPC5200B we need to set the special configuration delay in the
183 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
184 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
186 * "The SDelay should be written to a value of 0x00000004. It is
187 * required to account for changes caused by normal wafer processing
192 if ((SVR_MJREV(svr
) >= 2) &&
193 (PVR_MAJ(pvr
) == 1) && (PVR_MIN(pvr
) == 4)) {
195 *(vu_long
*)MPC5XXX_SDRAM_SDELAY
= 0x04;
196 __asm__
volatile ("sync");
199 gd
->ram_size
= dramsize
+ dramsize2
;
204 int checkboard (void)
206 puts ("Board: Sauter (Jupiter)\n");
210 void flash_preinit(void)
213 * Now, when we are in RAM, enable flash write
214 * access for detection process.
215 * Note that CS_BOOT cannot be cleared when
216 * executing in flash.
218 *(vu_long
*)MPC5XXX_BOOTCS_CFG
&= ~0x1; /* clear RO */
221 int board_early_init_r (void)
227 void flash_afterinit(ulong size
)
229 if (size
== 0x1000000) { /* adjust mapping */
230 *(vu_long
*)MPC5XXX_BOOTCS_START
= *(vu_long
*)MPC5XXX_CS0_START
=
231 START_REG(CONFIG_SYS_BOOTCS_START
| size
);
232 *(vu_long
*)MPC5XXX_BOOTCS_STOP
= *(vu_long
*)MPC5XXX_CS0_STOP
=
233 STOP_REG(CONFIG_SYS_BOOTCS_START
| size
, size
);
235 *(vu_long
*)MPC5XXX_ADDECR
&= ~(1 << 25); /* disable CS_BOOT */
236 *(vu_long
*)MPC5XXX_ADDECR
|= (1 << 16); /* enable CS0 */
239 int update_flash_size (int flash_size
)
241 flash_afterinit (flash_size
);
245 int board_early_init_f (void)
247 *(vu_long
*)MPC5XXX_BOOTCS_CFG
&= ~0x1; /* clear RO */
252 static struct pci_controller hose
;
254 extern void pci_mpc5xxx_init(struct pci_controller
*);
256 void pci_init_board(void)
258 pci_mpc5xxx_init(&hose
);
262 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
264 void init_ide_reset (void)
266 debug ("init_ide_reset\n");
268 /* Configure PSC1_4 as GPIO output for ATA reset */
269 *(vu_long
*) MPC5XXX_WU_GPIO_ENABLE
|= GPIO_PSC1_4
;
270 *(vu_long
*) MPC5XXX_WU_GPIO_DIR
|= GPIO_PSC1_4
;
272 *(vu_long
*) MPC5XXX_WU_GPIO_DATA_O
|= GPIO_PSC1_4
;
275 void ide_set_reset (int idereset
)
277 debug ("ide_reset(%d)\n", idereset
);
280 *(vu_long
*) MPC5XXX_WU_GPIO_DATA_O
&= ~GPIO_PSC1_4
;
281 /* Make a delay. MPC5200 spec says 25 usec min */
284 *(vu_long
*) MPC5XXX_WU_GPIO_DATA_O
|= GPIO_PSC1_4
;
289 #ifdef CONFIG_OF_BOARD_SETUP
290 int ft_board_setup(void *blob
, bd_t
*bd
)
292 ft_cpu_setup(blob
, bd
);
296 #endif /* CONFIG_OF_BOARD_SETUP */