board/keymile/km82xx/km82xx.c

   1 /*
   2  * (C) Copyright 2007 - 2008
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <mpc8260.h>
  10 #include <ioports.h>
  11 #include <malloc.h>
  12 #include <asm/io.h>
  13
  14 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  15 #include <libfdt.h>
  16 #endif
  17
  18 #include <i2c.h>
  19 #include "../common/common.h"
  20
  21 /*
  22  * I/O Port configuration table
  23  *
  24  * if conf is 1, then that port pin will be configured at boot time
  25  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  26  */
  27 const iop_conf_t iop_conf_tab[4][32] = {
  28
  29         /* Port A */
  30         {       /*            conf      ppar psor pdir podr pdat */
  31                 { 0,             0,   0,   0,   0,   0 }, /* PA31            */
  32                 { 0,             0,   0,   0,   0,   0 }, /* PA30            */
  33                 { 0,             0,   0,   0,   0,   0 }, /* PA29            */
  34                 { 0,             0,   0,   0,   0,   0 }, /* PA28            */
  35                 { 0,             0,   0,   0,   0,   0 }, /* PA27            */
  36                 { 0,             0,   0,   0,   0,   0 }, /* PA26            */
  37                 { 0,             0,   0,   0,   0,   0 }, /* PA25            */
  38                 { 0,             0,   0,   0,   0,   0 }, /* PA24            */
  39                 { 0,             0,   0,   0,   0,   0 }, /* PA23            */
  40                 { 0,             0,   0,   0,   0,   0 }, /* PA22            */
  41                 { 0,             0,   0,   0,   0,   0 }, /* PA21            */
  42                 { 0,             0,   0,   0,   0,   0 }, /* PA20            */
  43                 { 0,             0,   0,   0,   0,   0 }, /* PA19            */
  44                 { 0,             0,   0,   0,   0,   0 }, /* PA18            */
  45                 { 0,             0,   0,   0,   0,   0 }, /* PA17            */
  46                 { 0,             0,   0,   0,   0,   0 }, /* PA16            */
  47                 { 0,             0,   0,   0,   0,   0 }, /* PA15            */
  48                 { 0,             0,   0,   0,   0,   0 }, /* PA14            */
  49                 { 0,             0,   0,   0,   0,   0 }, /* PA13            */
  50                 { 0,             0,   0,   0,   0,   0 }, /* PA12            */
  51                 { 0,             0,   0,   0,   0,   0 }, /* PA11            */
  52                 { 0,             0,   0,   0,   0,   0 }, /* PA10            */
  53                 { 1,             1,   0,   1,   0,   0 }, /* PA9 SMC2 TxD    */
  54                 { 1,             1,   0,   0,   0,   0 }, /* PA8 SMC2 RxD    */
  55                 { 0,             0,   0,   0,   0,   0 }, /* PA7             */
  56                 { 0,             0,   0,   0,   0,   0 }, /* PA6             */
  57                 { 0,             0,   0,   0,   0,   0 }, /* PA5             */
  58                 { 0,             0,   0,   0,   0,   0 }, /* PA4             */
  59                 { 0,             0,   0,   0,   0,   0 }, /* PA3             */
  60                 { 0,             0,   0,   0,   0,   0 }, /* PA2             */
  61                 { 0,             0,   0,   0,   0,   0 }, /* PA1             */
  62                 { 0,             0,   0,   0,   0,   0 }  /* PA0             */
  63         },
  64
  65         /* Port B */
  66         {       /*            conf      ppar psor pdir podr pdat */
  67                 { 0,             0,   0,   0,   0,   0 }, /* PB31            */
  68                 { 0,             0,   0,   0,   0,   0 }, /* PB30            */
  69                 { 0,             0,   0,   0,   0,   0 }, /* PB29            */
  70                 { 0,             0,   0,   0,   0,   0 }, /* PB28            */
  71                 { 0,             0,   0,   0,   0,   0 }, /* PB27            */
  72                 { 0,             0,   0,   0,   0,   0 }, /* PB26            */
  73                 { 0,             0,   0,   0,   0,   0 }, /* PB25            */
  74                 { 0,             0,   0,   0,   0,   0 }, /* PB24            */
  75                 { 0,             0,   0,   0,   0,   0 }, /* PB23            */
  76                 { 0,             0,   0,   0,   0,   0 }, /* PB22            */
  77                 { 0,             0,   0,   0,   0,   0 }, /* PB21            */
  78                 { 0,             0,   0,   0,   0,   0 }, /* PB20            */
  79                 { 0,             0,   0,   0,   0,   0 }, /* PB19            */
  80                 { 0,             0,   0,   0,   0,   0 }, /* PB18            */
  81                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  82                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  83                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  84                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  85                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  86                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  87                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  88                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  89                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  90                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  91                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  92                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  93                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  94                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  95                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  96                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  97                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
  98                 { 0,             0,   0,   0,   0,   0 }  /* non-existent    */
  99         },
 100
 101         /* Port C */
 102         {       /*            conf      ppar psor pdir podr pdat */
 103                 { 0,             0,   0,   0,   0,   0 }, /* PC31            */
 104                 { 0,             0,   0,   0,   0,   0 }, /* PC30            */
 105                 { 0,             0,   0,   0,   0,   0 }, /* PC29            */
 106                 { 0,             0,   0,   0,   0,   0 }, /* PC28            */
 107                 { 0,             0,   0,   0,   0,   0 }, /* PC27            */
 108                 { 0,             0,   0,   0,   0,   0 }, /* PC26            */
 109                 { 1,             1,   0,   0,   0,   0 }, /* PC25 RxClk      */
 110                 { 1,             1,   0,   0,   0,   0 }, /* PC24 TxClk      */
 111                 { 0,             0,   0,   0,   0,   0 }, /* PC23            */
 112                 { 0,             0,   0,   0,   0,   0 }, /* PC22            */
 113                 { 0,             0,   0,   0,   0,   0 }, /* PC21            */
 114                 { 0,             0,   0,   0,   0,   0 }, /* PC20            */
 115                 { 0,             0,   0,   0,   0,   0 }, /* PC19            */
 116                 { 0,             0,   0,   0,   0,   0 }, /* PC18            */
 117                 { 0,             0,   0,   0,   0,   0 }, /* PC17            */
 118                 { 0,             0,   0,   0,   0,   0 }, /* PC16            */
 119                 { 0,             0,   0,   0,   0,   0 }, /* PC15            */
 120                 { 0,             0,   0,   0,   0,   0 }, /* PC14            */
 121                 { 0,             0,   0,   0,   0,   0 }, /* PC13            */
 122                 { 0,             0,   0,   0,   0,   0 }, /* PC12            */
 123                 { 0,             0,   0,   0,   0,   0 }, /* PC11            */
 124                 { 0,             0,   0,   0,   0,   0 }, /* PC10            */
 125                 { 1,             1,   0,   0,   0,   0 }, /* PC9  SCC4: CTS  */
 126                 { 1,             1,   0,   0,   0,   0 }, /* PC8  SCC4: CD   */
 127                 { 0,             0,   0,   0,   0,   0 }, /* PC7             */
 128                 { 0,             0,   0,   0,   0,   0 }, /* PC6             */
 129                 { 0,             0,   0,   0,   0,   0 }, /* PC5             */
 130                 { 0,             0,   0,   0,   0,   0 }, /* PC4             */
 131                 { 0,             0,   0,   0,   0,   0 }, /* PC3             */
 132                 { 0,             0,   0,   0,   0,   0 }, /* PC2             */
 133                 { 0,             0,   0,   0,   0,   0 }, /* PC1             */
 134                 { 0,             0,   0,   0,   0,   0 }, /* PC0             */
 135         },
 136
 137         /* Port D */
 138         {       /*            conf      ppar psor pdir podr pdat */
 139                 { 0,             0,   0,   0,   0,   0 }, /* PD31            */
 140                 { 0,             0,   0,   0,   0,   0 }, /* PD30            */
 141                 { 0,             0,   0,   0,   0,   0 }, /* PD29            */
 142                 { 0,             0,   0,   0,   0,   0 }, /* PD28            */
 143                 { 0,             0,   0,   0,   0,   0 }, /* PD27            */
 144                 { 0,             0,   0,   0,   0,   0 }, /* PD26            */
 145                 { 0,             0,   0,   0,   0,   0 }, /* PD25            */
 146                 { 0,             0,   0,   0,   0,   0 }, /* PD24            */
 147                 { 0,             0,   0,   0,   0,   0 }, /* PD23            */
 148                 { 1,             1,   0,   0,   0,   0 }, /* PD22 SCC4: RXD  */
 149                 { 1,             1,   0,   1,   0,   0 }, /* PD21 SCC4: TXD  */
 150                 { 1,             1,   0,   1,   0,   0 }, /* PD20 SCC4: RTS  */
 151                 { 0,             0,   0,   0,   0,   0 }, /* PD19            */
 152                 { 0,             0,   0,   0,   0,   0 }, /* PD18            */
 153                 { 0,             0,   0,   0,   0,   0 }, /* PD17            */
 154                 { 0,             0,   0,   0,   0,   0 }, /* PD16            */
 155 #if defined(CONFIG_HARD_I2C)
 156                 { 1,             1,   1,   0,   1,   0 }, /* PD15 I2C SDA    */
 157                 { 1,             1,   1,   0,   1,   0 }, /* PD14 I2C SCL    */
 158 #else
 159                 { 1,             0,   0,   0,   1,   1 }, /* PD15            */
 160                 { 1,             0,   0,   1,   1,   1 }, /* PD14            */
 161 #endif
 162                 { 0,             0,   0,   0,   0,   0 }, /* PD13            */
 163                 { 0,             0,   0,   0,   0,   0 }, /* PD12            */
 164                 { 0,             0,   0,   0,   0,   0 }, /* PD11            */
 165                 { 0,             0,   0,   0,   0,   0 }, /* PD10            */
 166                 { 0,             0,   0,   0,   0,   0 }, /* PD9             */
 167                 { 0,             0,   0,   0,   0,   0 }, /* PD8             */
 168                 { 0,             0,   0,   0,   0,   0 }, /* PD7             */
 169                 { 0,             0,   0,   0,   0,   0 }, /* PD6             */
 170                 { 0,             0,   0,   0,   0,   0 }, /* PD5             */
 171                 { 0,             0,   0,   0,   0,   0 }, /* PD4             */
 172                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 173                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 174                 { 0,             0,   0,   0,   0,   0 }, /* non-existent    */
 175                 { 0,             0,   0,   0,   0,   0 }  /* non-existent    */
 176         }
 177 };
 178
 179 /*
 180  * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 181  *
 182  * This routine performs standard 8260 initialization sequence
 183  * and calculates the available memory size. It may be called
 184  * several times to try different SDRAM configurations on both
 185  * 60x and local buses.
 186  */
 187 static long int try_init(memctl8260_t *memctl, ulong sdmr,
 188                                   ulong orx, uchar *base)
 189 {
 190         uchar c = 0xff;
 191         ulong maxsize, size;
 192         int i;
 193
 194         /*
 195          * We must be able to test a location outsize the maximum legal size
 196          * to find out THAT we are outside; but this address still has to be
 197          * mapped by the controller. That means, that the initial mapping has
 198          * to be (at least) twice as large as the maximum expected size.
 199          */
 200         maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
 201
 202         out_be32(&memctl->memc_or1, orx);
 203
 204         /*
 205          * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 206          *
 207          * "At system reset, initialization software must set up the
 208          *  programmable parameters in the memory controller banks registers
 209          *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
 210          *  system software should execute the following initialization sequence
 211          *  for each SDRAM device.
 212          *
 213          *  1. Issue a PRECHARGE-ALL-BANKS command
 214          *  2. Issue eight CBR REFRESH commands
 215          *  3. Issue a MODE-SET command to initialize the mode register
 216          *
 217          *  The initial commands are executed by setting P/LSDMR[OP] and
 218          *  accessing the SDRAM with a single-byte transaction."
 219          *
 220          * The appropriate BRx/ORx registers have already been set when we
 221          * get here. The SDRAM can be accessed at the address
 222          * CONFIG_SYS_SDRAM_BASE.
 223          */
 224
 225         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
 226         out_8(base, c);
 227
 228         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
 229         for (i = 0; i < 8; i++)
 230                 out_8(base, c);
 231
 232         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
 233         /* setting MR on address lines */
 234         out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
 235
 236         out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
 237         out_8(base, c);
 238
 239         size = get_ram_size((long *)base, maxsize);
 240         out_be32(&memctl->memc_or1, orx | ~(size - 1));
 241
 242         return size;
 243 }
 244
 245 #ifdef CONFIG_SYS_SDRAM_LIST
 246
 247 /*
 248  * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM
 249  * configurations therein (should be from high to lower) to find the
 250  * one actually matching the current configuration.
 251  * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are
 252  * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST
 253  * (defined as the initialization value for the array of struct sdram_conf_s)
 254  * will then be ORed with such base values.
 255  */
 256
 257 struct sdram_conf_s {
 258         ulong size;
 259         int or1;
 260         int psdmr;
 261 };
 262
 263 static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST;
 264
 265 static long probe_sdram(memctl8260_t *memctl)
 266 {
 267         int n = 0;
 268         long psize = 0;
 269
 270         for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) {
 271                 psize = try_init(memctl,
 272                         CONFIG_SYS_PSDMR | sdram_conf[n].psdmr,
 273                         CONFIG_SYS_OR1 | sdram_conf[n].or1,
 274                         (uchar *) CONFIG_SYS_SDRAM_BASE);
 275                 debug("Probing %ld bytes returned %ld\n",
 276                         sdram_conf[n].size, psize);
 277                 if (psize == sdram_conf[n].size)
 278                         break;
 279         }
 280         return psize;
 281 }
 282
 283 #else /* CONFIG_SYS_SDRAM_LIST */
 284
 285 static long probe_sdram(memctl8260_t *memctl)
 286 {
 287         return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
 288                                         (uchar *) CONFIG_SYS_SDRAM_BASE);
 289 }
 290 #endif /* CONFIG_SYS_SDRAM_LIST */
 291
 292
 293 phys_size_t initdram(int board_type)
 294 {
 295         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 296         memctl8260_t *memctl = &immap->im_memctl;
 297
 298         long psize;
 299
 300         out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
 301         out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
 302
 303         /* 60x SDRAM setup:
 304          */
 305         psize = probe_sdram(memctl);
 306
 307         icache_enable();
 308
 309         return psize;
 310 }
 311
 312 int checkboard(void)
 313 {
 314 #if defined(CONFIG_MGCOGE)
 315         puts("Board: Keymile mgcoge");
 316 #else
 317         puts("Board: Keymile mgcoge3ne");
 318 #endif
 319         if (ethernet_present())
 320                 puts(" with PIGGY.");
 321         puts("\n");
 322         return 0;
 323 }
 324
 325 int last_stage_init(void)
 326 {
 327         struct bfticu_iomap *base =
 328                 (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE;
 329         u8 dip_switch;
 330
 331         dip_switch = in_8(&base->mswitch);
 332         dip_switch &= BFTICU_DIPSWITCH_MASK;
 333         /* dip switch 'full reset' or 'db erase' */
 334         if (dip_switch & 0x1 || dip_switch & 0x2) {
 335                 /* start bootloader */
 336                 puts("DIP:   Enabled\n");
 337                 setenv("actual_bank", "0");
 338         }
 339         set_km_env();
 340         return 0;
 341 }
 342
 343 #ifdef CONFIG_MGCOGE3NE
 344 static void set_pin(int state, unsigned long mask);
 345
 346 /*
 347  * For mgcoge3ne boards, the mgcoge3un control is controlled from
 348  * a GPIO line on the PPC CPU. If bobcatreset is set the line
 349  * will toggle once what forces the mgocge3un part to restart
 350  * immediately.
 351  */
 352 static void handle_mgcoge3un_reset(void)
 353 {
 354         char *bobcatreset = getenv("bobcatreset");
 355         if (bobcatreset) {
 356                 if (strcmp(bobcatreset, "true") == 0) {
 357                         puts("Forcing bobcat reset\n");
 358                         set_pin(0, 0x00000004); /* clear PD29 to reset arm */
 359                         udelay(1000);
 360                         set_pin(1, 0x00000004);
 361                 } else
 362                         set_pin(1, 0x00000004); /* set PD29 to not reset arm */
 363         }
 364 }
 365 #endif
 366
 367 int ethernet_present(void)
 368 {
 369         struct km_bec_fpga *base =
 370                 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 371
 372         return in_8(&base->bprth) & PIGGY_PRESENT;
 373 }
 374
 375 /*
 376  * Early board initalization.
 377  */
 378 int board_early_init_r(void)
 379 {
 380         struct km_bec_fpga *base =
 381                 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
 382
 383         /* setup the UPIOx */
 384         /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
 385         out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
 386         /* SCC4 enable, halfduplex, FCC1 powerdown */
 387         out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
 388                 H_OPORTS_FCC1_PW_DWN));
 389
 390 #ifdef CONFIG_MGCOGE3NE
 391         handle_mgcoge3un_reset();
 392 #endif
 393         return 0;
 394 }
 395
 396 int hush_init_var(void)
 397 {
 398         ivm_read_eeprom();
 399         return 0;
 400 }
 401
 402 #define SDA_MASK        0x00010000
 403 #define SCL_MASK        0x00020000
 404
 405 static void set_pin(int state, unsigned long mask)
 406 {
 407         ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
 408
 409         if (state)
 410                 setbits_be32(&iop->pdat, mask);
 411         else
 412                 clrbits_be32(&iop->pdat, mask);
 413
 414         setbits_be32(&iop->pdir, mask);
 415 }
 416
 417 static int get_pin(unsigned long mask)
 418 {
 419         ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
 420
 421         clrbits_be32(&iop->pdir, mask);
 422         return 0 != (in_be32(&iop->pdat) & mask);
 423 }
 424
 425 void set_sda(int state)
 426 {
 427         set_pin(state, SDA_MASK);
 428 }
 429
 430 void set_scl(int state)
 431 {
 432         set_pin(state, SCL_MASK);
 433 }
 434
 435 int get_sda(void)
 436 {
 437         return get_pin(SDA_MASK);
 438 }
 439
 440 int get_scl(void)
 441 {
 442         return get_pin(SCL_MASK);
 443 }
 444
 445 #if defined(CONFIG_HARD_I2C)
 446 static void setports(int gpio)
 447 {
 448         ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
 449
 450         if (gpio) {
 451                 clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
 452                 clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
 453         } else {
 454                 setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
 455                 clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
 456                 setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
 457         }
 458 }
 459 #endif
 460 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 461 int ft_board_setup(void *blob, bd_t *bd)
 462 {
 463         ft_cpu_setup(blob, bd);
 464
 465         return 0;
 466 }
 467 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */