2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
11 * (C) Copyright 2008 - 2010
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
14 * SPDX-License-Identifier: GPL-2.0+
24 #include <asm/processor.h>
29 #include "../common/common.h"
31 DECLARE_GLOBAL_DATA_PTR
;
33 static uchar ivm_content
[CONFIG_SYS_IVM_EEPROM_MAX_LEN
];
35 const qe_iop_conf_t qe_iop_conf_tab
[] = {
36 /* port pin dir open_drain assign */
37 #if defined(CONFIG_MPC8360)
39 {0, 1, 3, 0, 2}, /* MDIO */
40 {0, 2, 1, 0, 1}, /* MDC */
43 {1, 14, 1, 0, 1}, /* TxD0 */
44 {1, 15, 1, 0, 1}, /* TxD1 */
45 {1, 20, 2, 0, 1}, /* RxD0 */
46 {1, 21, 2, 0, 1}, /* RxD1 */
47 {1, 18, 1, 0, 1}, /* TX_EN */
48 {1, 26, 2, 0, 1}, /* RX_DV */
49 {1, 27, 2, 0, 1}, /* RX_ER */
50 {1, 24, 2, 0, 1}, /* COL */
51 {1, 25, 2, 0, 1}, /* CRS */
52 {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
53 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
56 {5, 0, 1, 0, 2}, /* UART2_SOUT */
57 {5, 2, 1, 0, 1}, /* UART2_RTS */
58 {5, 3, 2, 0, 2}, /* UART2_SIN */
59 {5, 1, 2, 0, 3}, /* UART2_CTS */
60 #elif !defined(CONFIG_MPC8309)
62 {0, 16, 1, 0, 3}, /* LA00 */
63 {0, 17, 1, 0, 3}, /* LA01 */
64 {0, 18, 1, 0, 3}, /* LA02 */
65 {0, 19, 1, 0, 3}, /* LA03 */
66 {0, 20, 1, 0, 3}, /* LA04 */
67 {0, 21, 1, 0, 3}, /* LA05 */
68 {0, 22, 1, 0, 3}, /* LA06 */
69 {0, 23, 1, 0, 3}, /* LA07 */
70 {0, 24, 1, 0, 3}, /* LA08 */
71 {0, 25, 1, 0, 3}, /* LA09 */
72 {0, 26, 1, 0, 3}, /* LA10 */
73 {0, 27, 1, 0, 3}, /* LA11 */
74 {0, 28, 1, 0, 3}, /* LA12 */
75 {0, 29, 1, 0, 3}, /* LA13 */
76 {0, 30, 1, 0, 3}, /* LA14 */
77 {0, 31, 1, 0, 3}, /* LA15 */
80 {3, 4, 3, 0, 2}, /* MDIO */
81 {3, 5, 1, 0, 2}, /* MDC */
84 {1, 18, 1, 0, 1}, /* TxD0 */
85 {1, 19, 1, 0, 1}, /* TxD1 */
86 {1, 22, 2, 0, 1}, /* RxD0 */
87 {1, 23, 2, 0, 1}, /* RxD1 */
88 {1, 26, 2, 0, 1}, /* RxER */
89 {1, 28, 2, 0, 1}, /* Rx_DV */
90 {1, 30, 1, 0, 1}, /* TxEN */
91 {1, 31, 2, 0, 1}, /* CRS */
92 {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
96 {0, 0, 0, 0, QE_IOP_TAB_END
},
99 #if defined(CONFIG_SUVD3)
100 const uint upma_table
[] = {
101 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
102 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
103 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
104 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
105 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
106 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
107 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
108 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
109 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
110 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
111 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
112 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
113 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
114 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
115 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
116 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
120 static int piggy_present(void)
122 struct km_bec_fpga __iomem
*base
=
123 (struct km_bec_fpga __iomem
*)CONFIG_SYS_KMBEC_FPGA_BASE
;
125 return in_8(&base
->bprth
) & PIGGY_PRESENT
;
128 #if defined(CONFIG_KMVECT1)
129 int ethernet_present(void)
131 /* ethernet port connected to simple switch without piggy */
135 int ethernet_present(void)
137 return piggy_present();
142 int board_early_init_r(void)
144 struct km_bec_fpga
*base
=
145 (struct km_bec_fpga
*)CONFIG_SYS_KMBEC_FPGA_BASE
;
146 #if defined(CONFIG_SUVD3)
147 immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
148 fsl_lbc_t
*lbc
= &immap
->im_lbc
;
149 u32
*mxmr
= &lbc
->mamr
;
152 #if defined(CONFIG_MPC8360)
155 * Because of errata in the UCCs, we have to write to the reserved
156 * registers to slow the clocks down.
158 svid
= SVR_REV(mfspr(SVR
));
162 * MPC8360ECE.pdf QE_ENET10 table 4:
163 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
164 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
166 setbits_be32((void *)(CONFIG_SYS_IMMR
+ 0x14a8), 0x0c003000);
170 * MPC8360ECE.pdf QE_ENET10 table 4:
171 * IMMR + 0x14AC[24:27] = 1010
173 clrsetbits_be32((void *)(CONFIG_SYS_IMMR
+ 0x14ac),
174 0x00000050, 0x000000a0);
179 /* enable the PHY on the PIGGY */
180 setbits_8(&base
->pgy_eth
, 0x01);
181 /* enable the Unit LED (green) */
182 setbits_8(&base
->oprth
, WRL_BOOT
);
183 /* enable Application Buffer */
184 setbits_8(&base
->oprtl
, OPRTL_XBUFENA
);
186 #if defined(CONFIG_SUVD3)
187 /* configure UPMA for APP1 */
188 upmconfig(UPMA
, (uint
*) upma_table
,
189 sizeof(upma_table
) / sizeof(uint
));
190 out_be32(mxmr
, CONFIG_SYS_MAMR
);
195 int misc_init_r(void)
197 ivm_read_eeprom(ivm_content
, CONFIG_SYS_IVM_EEPROM_MAX_LEN
);
201 #if defined(CONFIG_KMVECT1)
202 #include <mv88e6352.h>
203 /* Marvell MV88E6122 switch configuration */
204 static struct mv88e_sw_reg extsw_conf
[] = {
205 /* port 1, FRONT_MDI, autoneg */
206 { PORT(1), PORT_PHY
, NO_SPEED_FOR
},
207 { PORT(1), PORT_CTRL
, FORWARDING
| EGRS_FLD_ALL
},
208 { PHY(1), PHY_1000_CTRL
, NO_ADV
},
209 { PHY(1), PHY_SPEC_CTRL
, AUTO_MDIX_EN
},
210 { PHY(1), PHY_CTRL
, PHY_100_MBPS
| AUTONEG_EN
| AUTONEG_RST
|
213 { PORT(2), PORT_CTRL
, PORT_DIS
},
214 { PHY(2), PHY_CTRL
, PHY_PWR_DOWN
},
215 { PHY(2), PHY_SPEC_CTRL
, SPEC_PWR_DOWN
},
216 /* port 3, BP_MII (CPU), PHY mode, 100BASE */
217 { PORT(3), PORT_CTRL
, FORWARDING
| EGRS_FLD_ALL
},
218 /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */
219 { PORT(4), PORT_STATUS
, NO_PHY_DETECT
},
220 { PORT(4), PORT_PHY
, SPEED_1000_FOR
},
221 { PORT(4), PORT_CTRL
, FORWARDING
| EGRS_FLD_ALL
},
222 /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */
223 { PORT(5), PORT_STATUS
, NO_PHY_DETECT
},
224 { PORT(5), PORT_PHY
, SPEED_1000_FOR
},
225 { PORT(5), PORT_CTRL
, FORWARDING
| EGRS_FLD_ALL
},
227 * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
228 * acc . MV-S300889-00D.pdf , clause 4.5
230 { PORT(5), 0x1A, 0xADB1 },
231 /* port 6, unused, this port has no phy */
232 { PORT(6), PORT_CTRL
, PORT_DIS
},
234 * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
235 * acc . MV-S300889-00D.pdf , clause 4.5
237 { PORT(5), 0x1A, 0xADB1 },
241 int last_stage_init(void)
243 #if defined(CONFIG_KMVECT1)
244 struct km_bec_fpga __iomem
*base
=
245 (struct km_bec_fpga __iomem
*)CONFIG_SYS_KMBEC_FPGA_BASE
;
248 /* Release mv88e6122 from reset */
249 tmp_reg
= in_8(&base
->res1
[0]) | 0x10; /* DIRECT3 register */
250 out_8(&base
->res1
[0], tmp_reg
); /* GP28 as output */
251 tmp_reg
= in_8(&base
->gprt3
) | 0x10; /* GP28 to high */
252 out_8(&base
->gprt3
, tmp_reg
);
254 /* configure MV88E6122 switch */
257 if (miiphy_set_current_dev(name
))
260 mv88e_sw_program(name
, CONFIG_KM_MVEXTSW_ADDR
, extsw_conf
,
261 ARRAY_SIZE(extsw_conf
));
263 mv88e_sw_reset(name
, CONFIG_KM_MVEXTSW_ADDR
);
265 if (piggy_present()) {
266 setenv("ethact", "UEC2");
267 setenv("netdev", "eth1");
268 puts("using PIGGY for network boot\n");
270 setenv("netdev", "eth0");
271 puts("using frontport for network boot\n");
275 #if defined(CONFIG_KMCOGE5NE)
276 struct bfticu_iomap
*base
=
277 (struct bfticu_iomap
*)CONFIG_SYS_BFTIC3_BASE
;
278 u8 dip_switch
= in_8((u8
*)&(base
->mswitch
)) & BFTICU_DIPSWITCH_MASK
;
280 if (dip_switch
!= 0) {
281 /* start bootloader */
282 puts("DIP: Enabled\n");
283 setenv("actual_bank", "0");
290 static int fixed_sdram(void)
292 immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
297 out_be32(&im
->sysconf
.ddrlaw
[0].ar
, (LAWAR_EN
| 0x1e));
298 out_be32(&im
->ddr
.csbnds
[0].csbnds
, (CONFIG_SYS_DDR_CS0_BNDS
) | 0x7f);
299 out_be32(&im
->ddr
.cs_config
[0], CONFIG_SYS_DDR_CS0_CONFIG
);
300 out_be32(&im
->ddr
.timing_cfg_0
, CONFIG_SYS_DDR_TIMING_0
);
301 out_be32(&im
->ddr
.timing_cfg_1
, CONFIG_SYS_DDR_TIMING_1
);
302 out_be32(&im
->ddr
.timing_cfg_2
, CONFIG_SYS_DDR_TIMING_2
);
303 out_be32(&im
->ddr
.timing_cfg_3
, CONFIG_SYS_DDR_TIMING_3
);
304 out_be32(&im
->ddr
.sdram_cfg
, CONFIG_SYS_DDR_SDRAM_CFG
);
305 out_be32(&im
->ddr
.sdram_cfg2
, CONFIG_SYS_DDR_SDRAM_CFG2
);
306 out_be32(&im
->ddr
.sdram_mode
, CONFIG_SYS_DDR_MODE
);
307 out_be32(&im
->ddr
.sdram_mode2
, CONFIG_SYS_DDR_MODE2
);
308 out_be32(&im
->ddr
.sdram_interval
, CONFIG_SYS_DDR_INTERVAL
);
309 out_be32(&im
->ddr
.sdram_clk_cntl
, CONFIG_SYS_DDR_CLK_CNTL
);
311 setbits_be32(&im
->ddr
.sdram_cfg
, SDRAM_CFG_MEM_EN
);
313 msize
= CONFIG_SYS_DDR_SIZE
<< 20;
314 disable_addr_trans();
315 msize
= get_ram_size(CONFIG_SYS_DDR_BASE
, msize
);
317 msize
/= (1024 * 1024);
318 if (CONFIG_SYS_DDR_SIZE
!= msize
) {
319 for (ddr_size
= msize
<< 20, ddr_size_log2
= 0;
321 ddr_size
= ddr_size
>> 1, ddr_size_log2
++)
324 out_be32(&im
->sysconf
.ddrlaw
[0].ar
,
325 (LAWAR_EN
| ((ddr_size_log2
- 1) & LAWAR_SIZE
)));
326 out_be32(&im
->ddr
.csbnds
[0].csbnds
,
327 (((msize
/ 16) - 1) & 0xff));
335 immap_t
*im
= (immap_t
*)CONFIG_SYS_IMMR
;
338 if ((in_be32(&im
->sysconf
.immrbar
) & IMMRBAR_BASE_ADDR
) != (u32
)im
)
341 out_be32(&im
->sysconf
.ddrlaw
[0].bar
,
342 CONFIG_SYS_DDR_BASE
& LAWBAR_BAR
);
343 msize
= fixed_sdram();
345 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
347 * Initialize DDR ECC byte
349 ddr_enable_ecc(msize
* 1024 * 1024);
352 /* return total bus SDRAM size(bytes) -- DDR */
353 gd
->ram_size
= msize
* 1024 * 1024;
360 puts("Board: Keymile " CONFIG_KM_BOARD_NAME
);
363 puts(" with PIGGY.");
368 int ft_board_setup(void *blob
, bd_t
*bd
)
370 ft_cpu_setup(blob
, bd
);
375 #if defined(CONFIG_HUSH_INIT_VAR)
376 int hush_init_var(void)
378 ivm_analyze_eeprom(ivm_content
, CONFIG_SYS_IVM_EEPROM_MAX_LEN
);
383 #if defined(CONFIG_POST)
384 int post_hotkeys_pressed(void)
387 struct km_bec_fpga
*base
=
388 (struct km_bec_fpga
*)CONFIG_SYS_KMBEC_FPGA_BASE
;
389 int testpin_reg
= in_8(&base
->CONFIG_TESTPIN_REG
);
390 testpin
= (testpin_reg
& CONFIG_TESTPIN_MASK
) != 0;
391 debug("post_hotkeys_pressed: %d\n", !testpin
);
395 ulong
post_word_load(void)
397 void* addr
= (ulong
*) (CPM_POST_WORD_ADDR
);
398 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong
)addr
, in_le32(addr
));
399 return in_le32(addr
);
402 void post_word_store(ulong value
)
404 void* addr
= (ulong
*) (CPM_POST_WORD_ADDR
);
405 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong
)addr
, value
);
406 out_le32(addr
, value
);
409 int arch_memory_test_prepare(u32
*vstart
, u32
*size
, phys_addr_t
*phys_offset
)
411 *vstart
= CONFIG_SYS_MEMTEST_START
;
412 *size
= CONFIG_SYS_MEMTEST_END
- CONFIG_SYS_MEMTEST_START
;
413 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart
, *size
);