board/keymile/km_arm/km_arm.c

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * (C) Copyright 2009
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * (C) Copyright 2010
  10  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #include <common.h>
  16 #include <i2c.h>
  17 #include <nand.h>
  18 #include <netdev.h>
  19 #include <miiphy.h>
  20 #include <spi.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/cpu.h>
  23 #include <asm/arch/soc.h>
  24 #include <asm/arch/mpp.h>
  25
  26 #include "../common/common.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 /*
  31  * BOCO FPGA definitions
  32  */
  33 #define BOCO            0x10
  34 #define REG_CTRL_H              0x02
  35 #define MASK_WRL_UNITRUN        0x01
  36 #define MASK_RBX_PGY_PRESENT    0x40
  37 #define REG_IRQ_CIRQ2           0x2d
  38 #define MASK_RBI_DEFECT_16      0x01
  39
  40 /*
  41  * PHY registers definitions
  42  */
  43 #define PHY_MARVELL_OUI                                 0x5043
  44 #define PHY_MARVELL_88E1118_MODEL                       0x0022
  45 #define PHY_MARVELL_88E1118R_MODEL                      0x0024
  46
  47 #define PHY_MARVELL_PAGE_REG                            0x0016
  48 #define PHY_MARVELL_DEFAULT_PAGE                        0x0000
  49
  50 #define PHY_MARVELL_88E1118R_LED_CTRL_PAGE              0x0003
  51 #define PHY_MARVELL_88E1118R_LED_CTRL_REG               0x0010
  52
  53 #define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED          0x1000
  54 #define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB       (0x7<<0)
  55 #define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT          (0x3<<4)
  56 #define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK         (0x0<<8)
  57
  58 /* Multi-Purpose Pins Functionality configuration */
  59 static const u32 kwmpp_config[] = {
  60         MPP0_NF_IO2,
  61         MPP1_NF_IO3,
  62         MPP2_NF_IO4,
  63         MPP3_NF_IO5,
  64         MPP4_NF_IO6,
  65         MPP5_NF_IO7,
  66         MPP6_SYSRST_OUTn,
  67 #if defined(KM_PCIE_RESET_MPP7)
  68         MPP7_GPO,
  69 #else
  70         MPP7_PEX_RST_OUTn,
  71 #endif
  72 #if defined(CONFIG_SYS_I2C_SOFT)
  73         MPP8_GPIO,              /* SDA */
  74         MPP9_GPIO,              /* SCL */
  75 #endif
  76 #if defined(CONFIG_HARD_I2C)
  77         MPP8_TW_SDA,
  78         MPP9_TW_SCK,
  79 #endif
  80         MPP10_UART0_TXD,
  81         MPP11_UART0_RXD,
  82         MPP12_GPO,              /* Reserved */
  83         MPP13_UART1_TXD,
  84         MPP14_UART1_RXD,
  85         MPP15_GPIO,             /* Not used */
  86         MPP16_GPIO,             /* Not used */
  87         MPP17_GPIO,             /* Reserved */
  88         MPP18_NF_IO0,
  89         MPP19_NF_IO1,
  90         MPP20_GPIO,
  91         MPP21_GPIO,
  92         MPP22_GPIO,
  93         MPP23_GPIO,
  94         MPP24_GPIO,
  95         MPP25_GPIO,
  96         MPP26_GPIO,
  97         MPP27_GPIO,
  98         MPP28_GPIO,
  99         MPP29_GPIO,
 100         MPP30_GPIO,
 101         MPP31_GPIO,
 102         MPP32_GPIO,
 103         MPP33_GPIO,
 104         MPP34_GPIO,             /* CDL1 (input) */
 105         MPP35_GPIO,             /* CDL2 (input) */
 106         MPP36_GPIO,             /* MAIN_IRQ (input) */
 107         MPP37_GPIO,             /* BOARD_LED */
 108         MPP38_GPIO,             /* Piggy3 LED[1] */
 109         MPP39_GPIO,             /* Piggy3 LED[2] */
 110         MPP40_GPIO,             /* Piggy3 LED[3] */
 111         MPP41_GPIO,             /* Piggy3 LED[4] */
 112         MPP42_GPIO,             /* Piggy3 LED[5] */
 113         MPP43_GPIO,             /* Piggy3 LED[6] */
 114         MPP44_GPIO,             /* Piggy3 LED[7], BIST_EN_L */
 115         MPP45_GPIO,             /* Piggy3 LED[8] */
 116         MPP46_GPIO,             /* Reserved */
 117         MPP47_GPIO,             /* Reserved */
 118         MPP48_GPIO,             /* Reserved */
 119         MPP49_GPIO,             /* SW_INTOUTn */
 120         0
 121 };
 122
 123 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 124
 125 #if defined(CONFIG_KM_MGCOGE3UN)
 126 /*
 127  * Wait for startup OK from mgcoge3ne
 128  */
 129 static int startup_allowed(void)
 130 {
 131         unsigned char buf;
 132
 133         /*
 134          * Read CIRQ16 bit (bit 0)
 135          */
 136         if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
 137                 printf("%s: Error reading Boco\n", __func__);
 138         else
 139                 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
 140                         return 1;
 141         return 0;
 142 }
 143 #endif
 144
 145 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
 146 /*
 147  * All boards with PIGGY4 connected via a simple switch have ethernet always
 148  * present.
 149  */
 150 int ethernet_present(void)
 151 {
 152         return 1;
 153 }
 154 #else
 155 int ethernet_present(void)
 156 {
 157         uchar   buf;
 158         int     ret = 0;
 159
 160         if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
 161                 printf("%s: Error reading Boco\n", __func__);
 162                 return -1;
 163         }
 164         if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
 165                 ret = 1;
 166
 167         return ret;
 168 }
 169 #endif
 170
 171 static int initialize_unit_leds(void)
 172 {
 173         /*
 174          * Init the unit LEDs per default they all are
 175          * ok apart from bootstat
 176          */
 177         uchar buf;
 178
 179         if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
 180                 printf("%s: Error reading Boco\n", __func__);
 181                 return -1;
 182         }
 183         buf |= MASK_WRL_UNITRUN;
 184         if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
 185                 printf("%s: Error writing Boco\n", __func__);
 186                 return -1;
 187         }
 188         return 0;
 189 }
 190
 191 static void set_bootcount_addr(void)
 192 {
 193         uchar buf[32];
 194         unsigned int bootcountaddr;
 195         bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
 196         sprintf((char *)buf, "0x%x", bootcountaddr);
 197         setenv("bootcountaddr", (char *)buf);
 198 }
 199
 200 int misc_init_r(void)
 201 {
 202 #if defined(CONFIG_KM_MGCOGE3UN)
 203         char *wait_for_ne;
 204         wait_for_ne = getenv("waitforne");
 205         if (wait_for_ne != NULL) {
 206                 if (strcmp(wait_for_ne, "true") == 0) {
 207                         int cnt = 0;
 208                         int abort = 0;
 209                         puts("NE go: ");
 210                         while (startup_allowed() == 0) {
 211                                 if (tstc()) {
 212                                         (void) getc(); /* consume input */
 213                                         abort = 1;
 214                                         break;
 215                                 }
 216                                 udelay(200000);
 217                                 cnt++;
 218                                 if (cnt == 5)
 219                                         puts("wait\b\b\b\b");
 220                                 if (cnt == 10) {
 221                                         cnt = 0;
 222                                         puts("    \b\b\b\b");
 223                                 }
 224                         }
 225                         if (abort == 1)
 226                                 printf("\nAbort waiting for ne\n");
 227                         else
 228                                 puts("OK\n");
 229                 }
 230         }
 231 #endif
 232
 233         ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
 234
 235         initialize_unit_leds();
 236         set_km_env();
 237         set_bootcount_addr();
 238         return 0;
 239 }
 240
 241 int board_early_init_f(void)
 242 {
 243 #if defined(CONFIG_SYS_I2C_SOFT)
 244         u32 tmp;
 245
 246         /* set the 2 bitbang i2c pins as output gpios */
 247         tmp = readl(MVEBU_GPIO0_BASE + 4);
 248         writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , MVEBU_GPIO0_BASE + 4);
 249 #endif
 250         /* adjust SDRAM size for bank 0 */
 251         mvebu_sdram_size_adjust(0);
 252         kirkwood_mpp_conf(kwmpp_config, NULL);
 253         return 0;
 254 }
 255
 256 int board_init(void)
 257 {
 258         /* address of boot parameters */
 259         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 260
 261         /*
 262          * The KM_FLASH_GPIO_PIN switches between using a
 263          * NAND or a SPI FLASH. Set this pin on start
 264          * to NAND mode.
 265          */
 266         kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
 267         kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
 268
 269 #if defined(CONFIG_SYS_I2C_SOFT)
 270         /*
 271          * Reinit the GPIO for I2C Bitbang driver so that the now
 272          * available gpio framework is consistent. The calls to
 273          * direction output in are not necessary, they are already done in
 274          * board_early_init_f
 275          */
 276         kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
 277         kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
 278 #endif
 279
 280 #if defined(CONFIG_SYS_EEPROM_WREN)
 281         kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
 282         kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
 283 #endif
 284
 285 #if defined(CONFIG_KM_FPGA_CONFIG)
 286         trigger_fpga_config();
 287 #endif
 288
 289         return 0;
 290 }
 291
 292 int board_late_init(void)
 293 {
 294 #if defined(CONFIG_KMCOGE5UN)
 295 /* I/O pin to erase flash RGPP09 = MPP43 */
 296 #define KM_FLASH_ERASE_ENABLE   43
 297         u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
 298
 299         /* if pin 1 do full erase */
 300         if (dip_switch != 0) {
 301                 /* start bootloader */
 302                 puts("DIP:   Enabled\n");
 303                 setenv("actual_bank", "0");
 304         }
 305 #endif
 306
 307 #if defined(CONFIG_KM_FPGA_CONFIG)
 308         wait_for_fpga_config();
 309         fpga_reset();
 310         toggle_eeprom_spi_bus();
 311 #endif
 312         return 0;
 313 }
 314
 315 int board_spi_claim_bus(struct spi_slave *slave)
 316 {
 317         kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
 318
 319         return 0;
 320 }
 321
 322 void board_spi_release_bus(struct spi_slave *slave)
 323 {
 324         kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
 325 }
 326
 327 #if (defined(CONFIG_KM_PIGGY4_88E6061))
 328
 329 #define PHY_LED_SEL_REG         0x18
 330 #define PHY_LED0_LINK           (0x5)
 331 #define PHY_LED1_ACT            (0x8<<4)
 332 #define PHY_LED2_INT            (0xe<<8)
 333 #define PHY_SPEC_CTRL_REG       0x1c
 334 #define PHY_RGMII_CLK_STABLE    (0x1<<10)
 335 #define PHY_CLSA                (0x1<<1)
 336
 337 /* Configure and enable MV88E3018 PHY */
 338 void reset_phy(void)
 339 {
 340         char *name = "egiga0";
 341         unsigned short reg;
 342
 343         if (miiphy_set_current_dev(name))
 344                 return;
 345
 346         /* RGMII clk transition on data stable */
 347         if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg))
 348                 printf("Error reading PHY spec ctrl reg\n");
 349         if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
 350                          reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
 351                 printf("Error writing PHY spec ctrl reg\n");
 352
 353         /* leds setup */
 354         if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
 355                          PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
 356                 printf("Error writing PHY LED reg\n");
 357
 358         /* reset the phy */
 359         miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 360 }
 361 #elif defined(CONFIG_KM_PIGGY4_88E6352)
 362
 363 #include <mv88e6352.h>
 364
 365 #if defined(CONFIG_KM_NUSA)
 366 struct mv88e_sw_reg extsw_conf[] = {
 367         /*
 368          * port 0, PIGGY4, autoneg
 369          * first the fix for the 1000Mbits Autoneg, this is from
 370          * a Marvell errata, the regs are undocumented
 371          */
 372         { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
 373         { PHY(0), PHY_STATUS, AN1000FIX },
 374         { PHY(0), PHY_PAGE, 0 },
 375         /* now the real port and phy configuration */
 376         { PORT(0), PORT_PHY, NO_SPEED_FOR },
 377         { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 378         { PHY(0), PHY_1000_CTRL, NO_ADV },
 379         { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
 380         { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
 381                 FULL_DUPLEX },
 382         /* port 1, unused */
 383         { PORT(1), PORT_CTRL, PORT_DIS },
 384         { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
 385         { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
 386         /* port 2, unused */
 387         { PORT(2), PORT_CTRL, PORT_DIS },
 388         { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
 389         { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
 390         /* port 3, unused */
 391         { PORT(3), PORT_CTRL, PORT_DIS },
 392         { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
 393         { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
 394         /* port 4, ICNEV, SerDes, SGMII */
 395         { PORT(4), PORT_STATUS, NO_PHY_DETECT },
 396         { PORT(4), PORT_PHY, SPEED_1000_FOR },
 397         { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 398         { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
 399         { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
 400         /* port 5, CPU_RGMII */
 401         { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
 402                 FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
 403                 FULL_DPX_FOR | SPEED_1000_FOR },
 404         { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
 405         /* port 6, unused, this port has no phy */
 406         { PORT(6), PORT_CTRL, PORT_DIS },
 407 };
 408 #else
 409 struct mv88e_sw_reg extsw_conf[] = {};
 410 #endif
 411
 412 void reset_phy(void)
 413 {
 414 #if defined(CONFIG_KM_MVEXTSW_ADDR)
 415         char *name = "egiga0";
 416
 417         if (miiphy_set_current_dev(name))
 418                 return;
 419
 420         mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
 421                 ARRAY_SIZE(extsw_conf));
 422         mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
 423 #endif
 424 }
 425
 426 #else
 427 /* Configure and enable MV88E1118 PHY on the piggy*/
 428 void reset_phy(void)
 429 {
 430         unsigned int oui;
 431         unsigned char model, rev;
 432
 433         char *name = "egiga0";
 434
 435         if (miiphy_set_current_dev(name))
 436                 return;
 437
 438         /* reset the phy */
 439         miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 440
 441         /* get PHY model */
 442         if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
 443                 return;
 444
 445         /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
 446         if ((oui == PHY_MARVELL_OUI) &&
 447             (model == PHY_MARVELL_88E1118R_MODEL)) {
 448                 /* set page register to 3 */
 449                 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
 450                                  PHY_MARVELL_PAGE_REG,
 451                                  PHY_MARVELL_88E1118R_LED_CTRL_PAGE))
 452                         printf("Error writing PHY page reg\n");
 453
 454                 /*
 455                  * leds setup as printed on PCB:
 456                  * LED2 (Link): 0x0 (On Link, Off No Link)
 457                  * LED1 (Activity): 0x3 (On Activity, Off No Activity)
 458                  * LED0 (Speed): 0x7 (On 1000 MBits, Off Else)
 459                  */
 460                 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
 461                                  PHY_MARVELL_88E1118R_LED_CTRL_REG,
 462                                  PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |
 463                                  PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |
 464                                  PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |
 465                                  PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))
 466                         printf("Error writing PHY LED reg\n");
 467
 468                 /* set page register back to 0 */
 469                 if (miiphy_write(name, CONFIG_PHY_BASE_ADR,
 470                                  PHY_MARVELL_PAGE_REG,
 471                                  PHY_MARVELL_DEFAULT_PAGE))
 472                         printf("Error writing PHY page reg\n");
 473         }
 474 }
 475 #endif
 476
 477
 478 #if defined(CONFIG_HUSH_INIT_VAR)
 479 int hush_init_var(void)
 480 {
 481         ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
 482         return 0;
 483 }
 484 #endif
 485
 486 #if defined(CONFIG_SYS_I2C_SOFT)
 487 void set_sda(int state)
 488 {
 489         I2C_ACTIVE;
 490         I2C_SDA(state);
 491 }
 492
 493 void set_scl(int state)
 494 {
 495         I2C_SCL(state);
 496 }
 497
 498 int get_sda(void)
 499 {
 500         I2C_TRISTATE;
 501         return I2C_READ;
 502 }
 503
 504 int get_scl(void)
 505 {
 506         return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
 507 }
 508 #endif
 509
 510 #if defined(CONFIG_POST)
 511
 512 #define KM_POST_EN_L    44
 513 #define POST_WORD_OFF   8
 514
 515 int post_hotkeys_pressed(void)
 516 {
 517 #if defined(CONFIG_KM_COGE5UN)
 518         return kw_gpio_get_value(KM_POST_EN_L);
 519 #else
 520         return !kw_gpio_get_value(KM_POST_EN_L);
 521 #endif
 522 }
 523
 524 ulong post_word_load(void)
 525 {
 526         void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
 527         return in_le32(addr);
 528
 529 }
 530 void post_word_store(ulong value)
 531 {
 532         void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
 533         out_le32(addr, value);
 534 }
 535
 536 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 537 {
 538         *vstart = CONFIG_SYS_SDRAM_BASE;
 539
 540         /* we go up to relocation plus a 1 MB margin */
 541         *size = CONFIG_SYS_TEXT_BASE - (1<<20);
 542
 543         return 0;
 544 }
 545 #endif
 546
 547 #if defined(CONFIG_SYS_EEPROM_WREN)
 548 int eeprom_write_enable(unsigned dev_addr, int state)
 549 {
 550         kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
 551
 552         return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
 553 }
 554 #endif