board/keymile/km_arm/km_arm.c

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * (C) Copyright 2009
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * (C) Copyright 2010
  10  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  28  * MA 02110-1301 USA
  29  */
  30
  31 #include <common.h>
  32 #include <i2c.h>
  33 #include <nand.h>
  34 #include <netdev.h>
  35 #include <miiphy.h>
  36 #include <spi.h>
  37 #include <asm/io.h>
  38 #include <asm/arch/cpu.h>
  39 #include <asm/arch/kirkwood.h>
  40 #include <asm/arch/mpp.h>
  41
  42 #include "../common/common.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /*
  47  * BOCO FPGA definitions
  48  */
  49 #define BOCO            0x10
  50 #define REG_CTRL_H              0x02
  51 #define MASK_WRL_UNITRUN        0x01
  52 #define MASK_RBX_PGY_PRESENT    0x40
  53 #define REG_IRQ_CIRQ2           0x2d
  54 #define MASK_RBI_DEFECT_16      0x01
  55
  56 /* Multi-Purpose Pins Functionality configuration */
  57 u32 kwmpp_config[] = {
  58         MPP0_NF_IO2,
  59         MPP1_NF_IO3,
  60         MPP2_NF_IO4,
  61         MPP3_NF_IO5,
  62         MPP4_NF_IO6,
  63         MPP5_NF_IO7,
  64         MPP6_SYSRST_OUTn,
  65         MPP7_PEX_RST_OUTn,
  66 #if defined(CONFIG_SOFT_I2C)
  67         MPP8_GPIO,              /* SDA */
  68         MPP9_GPIO,              /* SCL */
  69 #endif
  70 #if defined(CONFIG_HARD_I2C)
  71         MPP8_TW_SDA,
  72         MPP9_TW_SCK,
  73 #endif
  74         MPP10_UART0_TXD,
  75         MPP11_UART0_RXD,
  76         MPP12_GPO,              /* Reserved */
  77         MPP13_UART1_TXD,
  78         MPP14_UART1_RXD,
  79         MPP15_GPIO,             /* Not used */
  80         MPP16_GPIO,             /* Not used */
  81         MPP17_GPIO,             /* Reserved */
  82         MPP18_NF_IO0,
  83         MPP19_NF_IO1,
  84         MPP20_GPIO,
  85         MPP21_GPIO,
  86         MPP22_GPIO,
  87         MPP23_GPIO,
  88         MPP24_GPIO,
  89         MPP25_GPIO,
  90         MPP26_GPIO,
  91         MPP27_GPIO,
  92         MPP28_GPIO,
  93         MPP29_GPIO,
  94         MPP30_GPIO,
  95         MPP31_GPIO,
  96         MPP32_GPIO,
  97         MPP33_GPIO,
  98         MPP34_GPIO,             /* CDL1 (input) */
  99         MPP35_GPIO,             /* CDL2 (input) */
 100         MPP36_GPIO,             /* MAIN_IRQ (input) */
 101         MPP37_GPIO,             /* BOARD_LED */
 102         MPP38_GPIO,             /* Piggy3 LED[1] */
 103         MPP39_GPIO,             /* Piggy3 LED[2] */
 104         MPP40_GPIO,             /* Piggy3 LED[3] */
 105         MPP41_GPIO,             /* Piggy3 LED[4] */
 106         MPP42_GPIO,             /* Piggy3 LED[5] */
 107         MPP43_GPIO,             /* Piggy3 LED[6] */
 108         MPP44_GPIO,             /* Piggy3 LED[7], BIST_EN_L */
 109         MPP45_GPIO,             /* Piggy3 LED[8] */
 110         MPP46_GPIO,             /* Reserved */
 111         MPP47_GPIO,             /* Reserved */
 112         MPP48_GPIO,             /* Reserved */
 113         MPP49_GPIO,             /* SW_INTOUTn */
 114         0
 115 };
 116
 117 #if defined(CONFIG_MGCOGE3UN)
 118 /*
 119  * Wait for startup OK from mgcoge3ne
 120  */
 121 int startup_allowed(void)
 122 {
 123         unsigned char buf;
 124
 125         /*
 126          * Read CIRQ16 bit (bit 0)
 127          */
 128         if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
 129                 printf("%s: Error reading Boco\n", __func__);
 130         else
 131                 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
 132                         return 1;
 133         return 0;
 134 }
 135 #endif
 136
 137 #if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)| \
 138         defined(CONFIG_KM_PIGGY4_88E6352))
 139 /*
 140  * All boards with PIGGY4 connected via a simple switch have ethernet always
 141  * present.
 142  */
 143 int ethernet_present(void)
 144 {
 145         return 1;
 146 }
 147 #else
 148 int ethernet_present(void)
 149 {
 150         uchar   buf;
 151         int     ret = 0;
 152
 153         if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
 154                 printf("%s: Error reading Boco\n", __func__);
 155                 return -1;
 156         }
 157         if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
 158                 ret = 1;
 159
 160         return ret;
 161 }
 162 #endif
 163
 164 int initialize_unit_leds(void)
 165 {
 166         /*
 167          * Init the unit LEDs per default they all are
 168          * ok apart from bootstat
 169          */
 170         uchar buf;
 171
 172         if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
 173                 printf("%s: Error reading Boco\n", __func__);
 174                 return -1;
 175         }
 176         buf |= MASK_WRL_UNITRUN;
 177         if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
 178                 printf("%s: Error writing Boco\n", __func__);
 179                 return -1;
 180         }
 181         return 0;
 182 }
 183
 184 #if defined(CONFIG_BOOTCOUNT_LIMIT)
 185 void set_bootcount_addr(void)
 186 {
 187         uchar buf[32];
 188         unsigned int bootcountaddr;
 189         bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
 190         sprintf((char *)buf, "0x%x", bootcountaddr);
 191         setenv("bootcountaddr", (char *)buf);
 192 }
 193 #endif
 194
 195 int misc_init_r(void)
 196 {
 197         char *str;
 198         int mach_type;
 199
 200         str = getenv("mach_type");
 201         if (str != NULL) {
 202                 mach_type = simple_strtoul(str, NULL, 10);
 203                 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
 204                 gd->bd->bi_arch_number = mach_type;
 205         }
 206 #if defined(CONFIG_MGCOGE3UN)
 207         char *wait_for_ne;
 208         wait_for_ne = getenv("waitforne");
 209         if (wait_for_ne != NULL) {
 210                 if (strcmp(wait_for_ne, "true") == 0) {
 211                         int cnt = 0;
 212                         int abort = 0;
 213                         puts("NE go: ");
 214                         while (startup_allowed() == 0) {
 215                                 if (tstc()) {
 216                                         (void) getc(); /* consume input */
 217                                         abort = 1;
 218                                         break;
 219                                 }
 220                                 udelay(200000);
 221                                 cnt++;
 222                                 if (cnt == 5)
 223                                         puts("wait\b\b\b\b");
 224                                 if (cnt == 10) {
 225                                         cnt = 0;
 226                                         puts("    \b\b\b\b");
 227                                 }
 228                         }
 229                         if (abort == 1)
 230                                 printf("\nAbort waiting for ne\n");
 231                         else
 232                                 puts("OK\n");
 233                 }
 234         }
 235 #endif
 236
 237         initialize_unit_leds();
 238         set_km_env();
 239 #if defined(CONFIG_BOOTCOUNT_LIMIT)
 240         set_bootcount_addr();
 241 #endif
 242         return 0;
 243 }
 244
 245 int board_early_init_f(void)
 246 {
 247         u32 tmp;
 248
 249         kirkwood_mpp_conf(kwmpp_config, NULL);
 250
 251         /*
 252          * The FLASH_GPIO_PIN switches between using a
 253          * NAND or a SPI FLASH. Set this pin on start
 254          * to NAND mode.
 255          */
 256         tmp = readl(KW_GPIO0_BASE);
 257         writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
 258         tmp = readl(KW_GPIO0_BASE + 4);
 259         writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
 260
 261 #if defined(CONFIG_SOFT_I2C)
 262         /* init the GPIO for I2C Bitbang driver */
 263         kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
 264         kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
 265         kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
 266         kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
 267 #endif
 268 #if defined(CONFIG_SYS_EEPROM_WREN)
 269         kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
 270         kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
 271 #endif
 272 #if defined(CONFIG_KM_RECONFIG_XLX)
 273         /* trigger the reconfiguration of the xilinx fpga */
 274         kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);
 275         kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);
 276         kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);
 277 #endif
 278         return 0;
 279 }
 280
 281 int board_init(void)
 282 {
 283         /* address of boot parameters */
 284         gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 285
 286         return 0;
 287 }
 288
 289 int board_spi_claim_bus(struct spi_slave *slave)
 290 {
 291         kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
 292
 293         return 0;
 294 }
 295
 296 void board_spi_release_bus(struct spi_slave *slave)
 297 {
 298         kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
 299 }
 300
 301 int dram_init(void)
 302 {
 303         /* dram_init must store complete ramsize in gd->ram_size */
 304         /* Fix this */
 305         gd->ram_size = get_ram_size((void *)kw_sdram_bar(0),
 306                                 kw_sdram_bs(0));
 307         return 0;
 308 }
 309
 310 void dram_init_banksize(void)
 311 {
 312         int i;
 313
 314         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 315                 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
 316                 gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
 317                                                        kw_sdram_bs(i));
 318         }
 319 }
 320
 321 #if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
 322
 323 #define PHY_LED_SEL     0x18
 324 #define PHY_LED0_LINK   (0x5)
 325 #define PHY_LED1_ACT    (0x8<<4)
 326 #define PHY_LED2_INT    (0xe<<8)
 327 #define PHY_SPEC_CTRL   0x1c
 328 #define PHY_RGMII_CLK_STABLE    (0x1<<10)
 329 #define PHY_CLSA        (0x1<<1)
 330
 331 /* Configure and enable MV88E3018 PHY */
 332 void reset_phy(void)
 333 {
 334         char *name = "egiga0";
 335         unsigned short reg;
 336
 337         if (miiphy_set_current_dev(name))
 338                 return;
 339
 340         /* RGMII clk transition on data stable */
 341         if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, &reg) != 0)
 342                 printf("Error reading PHY spec ctrl reg\n");
 343         if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL,
 344                 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0)
 345                 printf("Error writing PHY spec ctrl reg\n");
 346
 347         /* leds setup */
 348         if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL,
 349                 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0)
 350                 printf("Error writing PHY LED reg\n");
 351
 352         /* reset the phy */
 353         miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 354 }
 355 #else
 356 /* Configure and enable MV88E1118 PHY on the piggy*/
 357 void reset_phy(void)
 358 {
 359         char *name = "egiga0";
 360
 361         if (miiphy_set_current_dev(name))
 362                 return;
 363
 364         /* reset the phy */
 365         miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 366 }
 367 #endif
 368
 369
 370 #if defined(CONFIG_HUSH_INIT_VAR)
 371 int hush_init_var(void)
 372 {
 373         ivm_read_eeprom();
 374         return 0;
 375 }
 376 #endif
 377
 378 #if defined(CONFIG_BOOTCOUNT_LIMIT)
 379 const ulong patterns[]      = { 0x00000000,
 380                                 0xFFFFFFFF,
 381                                 0xFF00FF00,
 382                                 0x0F0F0F0F,
 383                                 0xF0F0F0F0};
 384 const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns);
 385 const ulong OFFS_PATTERN    = 3;
 386 const ulong REPEAT_PATTERN  = 1000;
 387
 388 void bootcount_store(ulong a)
 389 {
 390         ulong *save_addr;
 391         ulong size = 0;
 392         int i;
 393
 394         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 395                 size += gd->bd->bi_dram[i].size;
 396         save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
 397         writel(a, save_addr);
 398         writel(BOOTCOUNT_MAGIC, &save_addr[1]);
 399
 400         for (i = 0; i < REPEAT_PATTERN; i++)
 401                 writel(patterns[i % NBR_OF_PATTERNS],
 402                         &save_addr[i+OFFS_PATTERN]);
 403
 404 }
 405
 406 ulong bootcount_load(void)
 407 {
 408         ulong *save_addr;
 409         ulong size = 0;
 410         ulong counter = 0;
 411         int i, tmp;
 412
 413         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 414                 size += gd->bd->bi_dram[i].size;
 415         save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
 416
 417         counter = readl(&save_addr[0]);
 418
 419         /* Is the counter reliable, check in the big pattern for bit errors */
 420         for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) {
 421                 tmp = readl(&save_addr[i+OFFS_PATTERN]);
 422                 if (tmp != patterns[i % NBR_OF_PATTERNS])
 423                         counter = 0;
 424         }
 425         return counter;
 426 }
 427 #endif
 428
 429 #if defined(CONFIG_SOFT_I2C)
 430 void set_sda(int state)
 431 {
 432         I2C_ACTIVE;
 433         I2C_SDA(state);
 434 }
 435
 436 void set_scl(int state)
 437 {
 438         I2C_SCL(state);
 439 }
 440
 441 int get_sda(void)
 442 {
 443         I2C_TRISTATE;
 444         return I2C_READ;
 445 }
 446
 447 int get_scl(void)
 448 {
 449         return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
 450 }
 451 #endif
 452
 453 #if defined(CONFIG_POST)
 454
 455 #define KM_POST_EN_L    44
 456 #define POST_WORD_OFF   8
 457
 458 int post_hotkeys_pressed(void)
 459 {
 460 #if defined(CONFIG_KM_COGE5UN)
 461         return kw_gpio_get_value(KM_POST_EN_L);
 462 #else
 463         return !kw_gpio_get_value(KM_POST_EN_L);
 464 #endif
 465 }
 466
 467 ulong post_word_load(void)
 468 {
 469         void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
 470         return in_le32(addr);
 471
 472 }
 473 void post_word_store(ulong value)
 474 {
 475         void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
 476         out_le32(addr, value);
 477 }
 478
 479 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
 480 {
 481         *vstart = CONFIG_SYS_SDRAM_BASE;
 482
 483         /* we go up to relocation plus a 1 MB margin */
 484         *size = CONFIG_SYS_TEXT_BASE - (1<<20);
 485
 486         return 0;
 487 }
 488 #endif
 489
 490 #if defined(CONFIG_SYS_EEPROM_WREN)
 491 int eeprom_write_enable(unsigned dev_addr, int state)
 492 {
 493         kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
 494
 495         return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
 496 }
 497 #endif