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1 /*
2 * (C) Copyright 2013 Keymile AG
3 * Valentin Longchamp <valentin.longchamp@keymile.com>
4 *
5 * Copyright 2011,2012 Freescale Semiconductor, Inc.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <command.h>
12 #include <netdev.h>
13 #include <linux/compiler.h>
14 #include <asm/mmu.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
17 #include <asm/immap_85xx.h>
18 #include <asm/fsl_law.h>
19 #include <asm/fsl_serdes.h>
20 #include <asm/fsl_portals.h>
21 #include <asm/fsl_liodn.h>
22 #include <fm_eth.h>
23
24 #include "../common/common.h"
25 #include "kmp204x.h"
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 int checkboard(void)
30 {
31 printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
32
33 return 0;
34 }
35
36 /* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
37 * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
38 * For I2C only the low state is activly driven and high state is pulled-up
39 * by a resistor. Therefore the deblock GPIOs are used
40 * -> as an active output to drive a low state
41 * -> as an open-drain input to have a pulled-up high state
42 */
43
44 /* QRIO GPIOs used for deblocking */
45 #define DEBLOCK_PORT1 GPIO_A
46 #define DEBLOCK_SCL1 20
47 #define DEBLOCK_SDA1 21
48
49 /* By default deblock GPIOs are floating */
50 static void i2c_deblock_gpio_cfg(void)
51 {
52 /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
53 qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
54 qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
55
56 qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
57 qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
58 }
59
60 void set_sda(int state)
61 {
62 qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
63 }
64
65 void set_scl(int state)
66 {
67 qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
68 }
69
70 int get_sda(void)
71 {
72 return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
73 }
74
75 int get_scl(void)
76 {
77 return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
78 }
79
80
81 #define ZL30158_RST 8
82 #define ZL30343_RST 9
83
84 int board_early_init_f(void)
85 {
86 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
87
88 /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
89 setbits_be32(&gur->ddrclkdr, 0x001f000f);
90
91 /* take the Zarlinks out of reset as soon as possible */
92 qrio_prst(ZL30158_RST, false, false);
93 qrio_prst(ZL30343_RST, false, false);
94
95 /* and set their reset to power-up only */
96 qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
97 qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
98
99 return 0;
100 }
101
102 int board_early_init_r(void)
103 {
104 int ret = 0;
105 /* Flush d-cache and invalidate i-cache of any FLASH data */
106 flush_dcache();
107 invalidate_icache();
108
109 set_liodns();
110 setup_portals();
111
112 ret = trigger_fpga_config();
113 if (ret)
114 printf("error triggering PCIe FPGA config\n");
115
116 /* enable the Unit LED (red) & Boot LED (on) */
117 qrio_set_leds();
118
119 return ret;
120 }
121
122 unsigned long get_board_sys_clk(unsigned long dummy)
123 {
124 return 66666666;
125 }
126
127 int misc_init_f(void)
128 {
129 /* configure QRIO pis for i2c deblocking */
130 i2c_deblock_gpio_cfg();
131
132 return 0;
133 }
134
135 #define NUM_SRDS_BANKS 2
136 #define PHY_RST 15
137
138 int misc_init_r(void)
139 {
140 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
141 u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
142 SRDS_PLLCR0_RFCK_SEL_125};
143 unsigned int i;
144
145 /* check SERDES reference clocks */
146 for (i = 0; i < NUM_SRDS_BANKS; i++) {
147 u32 actual = in_be32(&regs->bank[i].pllcr0);
148 actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
149 if (actual != expected[i]) {
150 printf("Warning: SERDES bank %u expects reference \
151 clock %sMHz, but actual is %sMHz\n", i + 1,
152 serdes_clock_to_string(expected[i]),
153 serdes_clock_to_string(actual));
154 }
155 }
156
157 /* take the mgmt eth phy out of reset */
158 qrio_prst(PHY_RST, false, false);
159
160 return 0;
161 }
162
163 #if defined(CONFIG_HUSH_INIT_VAR)
164 int hush_init_var(void)
165 {
166 ivm_read_eeprom();
167 return 0;
168 }
169 #endif
170
171 #if defined(CONFIG_LAST_STAGE_INIT)
172 int last_stage_init(void)
173 {
174 set_km_env();
175 return 0;
176 }
177 #endif
178
179 #ifdef CONFIG_SYS_DPAA_FMAN
180 void fdt_fixup_fman_mac_addresses(void *blob)
181 {
182 int node, i, ret;
183 char *tmp, *end;
184 unsigned char mac_addr[6];
185
186 /* get the mac addr from env */
187 tmp = getenv("ethaddr");
188 if (!tmp) {
189 printf("ethaddr env variable not defined\n");
190 return;
191 }
192 for (i = 0; i < 6; i++) {
193 mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
194 if (tmp)
195 tmp = (*end) ? end+1 : end;
196 }
197
198 /* find the correct fdt ethernet path and correct it */
199 node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
200 if (node < 0) {
201 printf("no /soc/fman/ethernet path offset\n");
202 return;
203 }
204 ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
205 if (ret) {
206 printf("error setting local-mac-address property\n");
207 return;
208 }
209 }
210 #endif
211
212 void ft_board_setup(void *blob, bd_t *bd)
213 {
214 phys_addr_t base;
215 phys_size_t size;
216
217 ft_cpu_setup(blob, bd);
218
219 base = getenv_bootm_low();
220 size = getenv_bootm_size();
221
222 fdt_fixup_memory(blob, (u64)base, (u64)size);
223
224 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
225 fdt_fixup_dr_usb(blob, bd);
226 #endif
227
228 #ifdef CONFIG_PCI
229 pci_of_setup(blob, bd);
230 #endif
231
232 fdt_fixup_liodn(blob);
233 #ifdef CONFIG_SYS_DPAA_FMAN
234 fdt_fixup_fman_ethernet(blob);
235 fdt_fixup_fman_mac_addresses(blob);
236 #endif
237 }