board/keymile/mgcoge/mgcoge.c

   1 /*
   2  * (C) Copyright 2007 - 2008
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc8260.h>
  26 #include <ioports.h>
  27 #include <malloc.h>
  28
  29 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  30 #include <libfdt.h>
  31 #endif
  32
  33 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
  34 #include <i2c.h>
  35 #endif
  36
  37 extern int ivm_read_eeprom (void);
  38 /*
  39  * I/O Port configuration table
  40  *
  41  * if conf is 1, then that port pin will be configured at boot time
  42  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  43  */
  44 const iop_conf_t iop_conf_tab[4][32] = {
  45
  46     /* Port A */
  47     {   /*            conf      ppar psor pdir podr pdat */
  48         /* PA31 */ { 0,          0,   0,   0,   0,   0 }, /* PA31            */
  49         /* PA30 */ { 0,          0,   0,   0,   0,   0 }, /* PA30            */
  50         /* PA29 */ { 0,          0,   0,   0,   0,   0 }, /* PA29            */
  51         /* PA28 */ { 0,          0,   0,   0,   0,   0 }, /* PA28            */
  52         /* PA27 */ { 0,          0,   0,   0,   0,   0 }, /* PA27            */
  53         /* PA26 */ { 0,          0,   0,   0,   0,   0 }, /* PA26            */
  54         /* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
  55         /* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
  56         /* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
  57         /* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
  58         /* PA21 */ { 0,          0,   0,   0,   0,   0 }, /* PA21            */
  59         /* PA20 */ { 0,          0,   0,   0,   0,   0 }, /* PA20            */
  60         /* PA19 */ { 0,          0,   0,   0,   0,   0 }, /* PA19            */
  61         /* PA18 */ { 0,          0,   0,   0,   0,   0 }, /* PA18            */
  62         /* PA17 */ { 0,          0,   0,   0,   0,   0 }, /* PA17            */
  63         /* PA16 */ { 0,          0,   0,   0,   0,   0 }, /* PA16            */
  64         /* PA15 */ { 0,          0,   0,   0,   0,   0 }, /* PA15            */
  65         /* PA14 */ { 0,          0,   0,   0,   0,   0 }, /* PA14            */
  66         /* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
  67         /* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
  68         /* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
  69         /* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10            */
  70         /* PA9  */ { 1,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
  71         /* PA8  */ { 1,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
  72         /* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
  73         /* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
  74         /* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
  75         /* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
  76         /* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
  77         /* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
  78         /* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
  79         /* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
  80     },
  81
  82     /* Port B */
  83     {   /*            conf      ppar psor pdir podr pdat */
  84         /* PB31 */ { 0,          0,   0,   0,   0,   0 }, /* PB31            */
  85         /* PB30 */ { 0,          0,   0,   0,   0,   0 }, /* PB30            */
  86         /* PB29 */ { 0,          0,   0,   0,   0,   0 }, /* PB29            */
  87         /* PB28 */ { 0,          0,   0,   0,   0,   0 }, /* PB28            */
  88         /* PB27 */ { 0,          0,   0,   0,   0,   0 }, /* PB27            */
  89         /* PB26 */ { 0,          0,   0,   0,   0,   0 }, /* PB26            */
  90         /* PB25 */ { 0,          0,   0,   0,   0,   0 }, /* PB25            */
  91         /* PB24 */ { 0,          0,   0,   0,   0,   0 }, /* PB24            */
  92         /* PB23 */ { 0,          0,   0,   0,   0,   0 }, /* PB23            */
  93         /* PB22 */ { 0,          0,   0,   0,   0,   0 }, /* PB22            */
  94         /* PB21 */ { 0,          0,   0,   0,   0,   0 }, /* PB21            */
  95         /* PB20 */ { 0,          0,   0,   0,   0,   0 }, /* PB20            */
  96         /* PB19 */ { 0,          0,   0,   0,   0,   0 }, /* PB19            */
  97         /* PB18 */ { 0,          0,   0,   0,   0,   0 }, /* PB18            */
  98         /* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
  99         /* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 100         /* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 101         /* PB14 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 102         /* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 103         /* PB12 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 104         /* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 105         /* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 106         /* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 107         /* PB8  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 108         /* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 109         /* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 110         /* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 111         /* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 112         /* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 113         /* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 114         /* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 115         /* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
 116     },
 117
 118     /* Port C */
 119     {   /*            conf      ppar psor pdir podr pdat */
 120         /* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
 121         /* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
 122         /* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
 123         /* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
 124         /* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
 125         /* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
 126         /* PC25 */ { 1,          1,   0,   0,   0,   0 }, /* SCC4 RxClk      */
 127         /* PC24 */ { 1,          1,   0,   0,   0,   0 }, /* SCC4 TxClk      */
 128         /* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
 129         /* PC22 */ { 0,          0,   0,   0,   0,   0 }, /* PC22            */
 130         /* PC21 */ { 0,          0,   0,   0,   0,   0 }, /* PC21            */
 131         /* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
 132         /* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19            */
 133         /* PC18 */ { 0,          0,   0,   0,   0,   0 }, /* PC18            */
 134         /* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17            */
 135         /* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
 136         /* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
 137         /* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
 138         /* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
 139         /* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12            */
 140         /* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
 141         /* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
 142         /* PC9  */ { 1,          1,   0,   0,   0,   0 }, /* SCC4: CTS       */
 143         /* PC8  */ { 1,          1,   0,   0,   0,   0 }, /* SCC4: CD        */
 144         /* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
 145         /* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
 146         /* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5             */
 147         /* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4             */
 148         /* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
 149         /* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
 150         /* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
 151         /* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
 152     },
 153
 154     /* Port D */
 155     {   /*            conf      ppar psor pdir podr pdat */
 156         /* PD31 */ { 0,          0,   0,   0,   0,   0 }, /* PD31            */
 157         /* PD30 */ { 0,          0,   0,   0,   0,   0 }, /* PD30            */
 158         /* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
 159         /* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
 160         /* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
 161         /* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
 162         /* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
 163         /* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
 164         /* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
 165         /* PD22 */ { 1,          1,   0,   0,   0,   0 }, /* SCC4: RXD       */
 166         /* PD21 */ { 1,          1,   0,   1,   0,   0 }, /* SCC4: TXD       */
 167         /* PD20 */ { 1,          1,   0,   1,   0,   0 }, /* SCC4: RTS       */
 168         /* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
 169         /* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
 170         /* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
 171         /* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
 172 #if defined(CONFIG_HARD_I2C)
 173         /* PD15 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SDA         */
 174         /* PD14 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SCL         */
 175 #else
 176         /* PD15 */ { 1,          0,   0,   0,   1,   1 }, /* PD15            */
 177         /* PD14 */ { 1,          0,   0,   1,   1,   1 }, /* PD14            */
 178 #endif
 179         /* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
 180         /* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
 181         /* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
 182         /* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
 183         /* PD9  */ { 0,          0,   0,   0,   0,   0 }, /* PD9             */
 184         /* PD8  */ { 0,          0,   0,   0,   0,   0 }, /* PD8             */
 185         /* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
 186         /* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
 187         /* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
 188         /* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
 189         /* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 190         /* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 191         /* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 192         /* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
 193     }
 194 };
 195
 196 /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
 197  *
 198  * This routine performs standard 8260 initialization sequence
 199  * and calculates the available memory size. It may be called
 200  * several times to try different SDRAM configurations on both
 201  * 60x and local buses.
 202  */
 203 static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
 204                                                   ulong orx, volatile uchar * base)
 205 {
 206         volatile uchar c = 0xff;
 207         volatile uint *sdmr_ptr;
 208         volatile uint *orx_ptr;
 209         ulong maxsize, size;
 210         int i;
 211
 212         /* We must be able to test a location outsize the maximum legal size
 213          * to find out THAT we are outside; but this address still has to be
 214          * mapped by the controller. That means, that the initial mapping has
 215          * to be (at least) twice as large as the maximum expected size.
 216          */
 217         maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
 218
 219         sdmr_ptr = &memctl->memc_psdmr;
 220         orx_ptr = &memctl->memc_or1;
 221
 222         *orx_ptr = orx;
 223
 224         /*
 225          * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
 226          *
 227          * "At system reset, initialization software must set up the
 228          *  programmable parameters in the memory controller banks registers
 229          *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
 230          *  system software should execute the following initialization sequence
 231          *  for each SDRAM device.
 232          *
 233          *  1. Issue a PRECHARGE-ALL-BANKS command
 234          *  2. Issue eight CBR REFRESH commands
 235          *  3. Issue a MODE-SET command to initialize the mode register
 236          *
 237          *  The initial commands are executed by setting P/LSDMR[OP] and
 238          *  accessing the SDRAM with a single-byte transaction."
 239          *
 240          * The appropriate BRx/ORx registers have already been set when we
 241          * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 242          */
 243
 244         *sdmr_ptr = sdmr | PSDMR_OP_PREA;
 245         *base = c;
 246
 247         *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
 248         for (i = 0; i < 8; i++)
 249                 *base = c;
 250
 251         *sdmr_ptr = sdmr | PSDMR_OP_MRW;
 252         *(base + CONFIG_SYS_MRS_OFFS) = c;      /* setting MR on address lines */
 253
 254         *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 255         *base = c;
 256
 257         size = get_ram_size ((long *)base, maxsize);
 258         *orx_ptr = orx | ~(size - 1);
 259
 260         return (size);
 261 }
 262
 263 phys_size_t initdram (int board_type)
 264 {
 265         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 266         volatile memctl8260_t *memctl = &immap->im_memctl;
 267
 268         long psize;
 269
 270         memctl->memc_psrt = CONFIG_SYS_PSRT;
 271         memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 272
 273 #ifndef CONFIG_SYS_RAMBOOT
 274         /* 60x SDRAM setup:
 275          */
 276         psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
 277                                                   (uchar *) CONFIG_SYS_SDRAM_BASE);
 278 #endif /* CONFIG_SYS_RAMBOOT */
 279
 280         icache_enable ();
 281
 282         return (psize);
 283 }
 284
 285 int checkboard(void)
 286 {
 287         puts ("Board: mgcoge\n");
 288
 289         return 0;
 290 }
 291
 292 /*
 293  * Early board initalization.
 294  */
 295 int board_early_init_r (void)
 296 {
 297         /* setup the UPIOx */
 298         *(char *)(CONFIG_SYS_PIGGY_BASE + 0x02) = 0xc0;
 299         *(char *)(CONFIG_SYS_PIGGY_BASE + 0x03) = 0x15;
 300         return 0;
 301 }
 302
 303 int hush_init_var (void)
 304 {
 305         ivm_read_eeprom ();
 306         return 0;
 307 }
 308
 309 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
 310 /*
 311  * update "memory" property in the blob
 312  */
 313 void ft_blob_update (void *blob, bd_t *bd)
 314 {
 315         int ret, nodeoffset = 0;
 316         ulong memory_data[2] = {0};
 317         ulong flash_data[8] = {0};
 318
 319         memory_data[0] = cpu_to_be32 (bd->bi_memstart);
 320         memory_data[1] = cpu_to_be32 (bd->bi_memsize);
 321
 322         nodeoffset = fdt_path_offset (blob, "/memory");
 323         if (nodeoffset >= 0) {
 324                 ret = fdt_setprop (blob, nodeoffset, "reg", memory_data,
 325                                         sizeof (memory_data));
 326         if (ret < 0)
 327                 printf ("ft_blob_update(): cannot set /memory/reg "
 328                         "property err:%s\n", fdt_strerror (ret));
 329         } else {
 330                 /* memory node is required in dts */
 331                 printf ("ft_blob_update(): cannot find /memory node "
 332                         "err:%s\n", fdt_strerror (nodeoffset));
 333         }
 334         /* update Flash addr, size */
 335         flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
 336         flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE);
 337         flash_data[4] = cpu_to_be32 (1);
 338         flash_data[5] = cpu_to_be32 (0);
 339         flash_data[6] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE_1);
 340         flash_data[7] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE_1);
 341         nodeoffset = fdt_path_offset (blob, "/localbus");
 342         if (nodeoffset >= 0) {
 343                 ret = fdt_setprop (blob, nodeoffset, "ranges", flash_data,
 344                                         sizeof (flash_data));
 345         if (ret < 0)
 346                 printf ("ft_blob_update(): cannot set /localbus/ranges "
 347                         "property err:%s\n", fdt_strerror (ret));
 348         } else {
 349                 /* memory node is required in dts */
 350                 printf ("ft_blob_update(): cannot find /localbus node "
 351                         "err:%s\n", fdt_strerror (nodeoffset));
 352         }
 353         /* MAC Adresse */
 354         nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet");
 355         if (nodeoffset >= 0) {
 356                 ret = fdt_setprop (blob, nodeoffset, "mac-address", bd->bi_enetaddr,
 357                                         sizeof (uchar) * 6);
 358         if (ret < 0)
 359                 printf ("ft_blob_update(): cannot set /soc/cpm/ethernet/mac-address "
 360                         "property err:%s\n", fdt_strerror (ret));
 361         } else {
 362                 /* memory node is required in dts */
 363                 printf ("ft_blob_update(): cannot find /soc/cpm/ethernet node "
 364                         "err:%s\n", fdt_strerror (nodeoffset));
 365         }
 366
 367 }
 368
 369 void ft_board_setup (void *blob, bd_t *bd)
 370 {
 371         ft_cpu_setup (blob, bd);
 372         ft_blob_update (blob, bd);
 373 }
 374 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */