1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
4 * (C) Copyright 2012 Renesas Solutions Corp.
11 #include <asm/arch/sys_proto.h>
16 DECLARE_GLOBAL_DATA_PTR
;
18 #define CS0BCR_D (0x06C00400)
19 #define CS4BCR_D (0x16c90400)
20 #define CS0WCR_D (0x55062C42)
21 #define CS4WCR_D (0x1e071dc3)
23 #define CMNCR_BROMMD0 (1 << 21)
24 #define CMNCR_BROMMD1 (1 << 22)
25 #define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1)
26 #define VCLKCR1_D (0x27)
28 #define SMSTPCR1_CMT0 (1 << 24)
29 #define SMSTPCR1_I2C0 (1 << 16)
30 #define SMSTPCR3_USB (1 << 22)
31 #define SMSTPCR3_I2C1 (1 << 23)
33 #define PORT32CR (0xE6051020)
34 #define PORT33CR (0xE6051021)
35 #define PORT34CR (0xE6051022)
36 #define PORT35CR (0xE6051023)
38 static int cmp_loop(u32
*addr
, u32 data
, u32 cmp
)
46 if ((value
& data
) == cmp
) {
56 /* SBSC Init function */
57 static void sbsc_init(struct sh73a0_sbsc
*sbsc
)
59 writel(readl(&sbsc
->dllcnt0
)|0x2, &sbsc
->dllcnt0
);
60 writel(0x5, &sbsc
->sdgencnt
);
61 cmp_loop(&sbsc
->sdgencnt
, 0xffffffff, 0x0);
63 writel(0xacc90159, &sbsc
->sdcr0
);
64 writel(0x00010059, &sbsc
->sdcr1
);
65 writel(0x50874114, &sbsc
->sdwcrc0
);
66 writel(0x33199b37, &sbsc
->sdwcrc1
);
67 writel(0x008f2313, &sbsc
->sdwcrc2
);
68 writel(0x31020707, &sbsc
->sdwcr00
);
69 writel(0x0017040a, &sbsc
->sdwcr01
);
70 writel(0x31020707, &sbsc
->sdwcr10
);
71 writel(0x0017040a, &sbsc
->sdwcr11
);
72 writel(0x055557ff, &sbsc
->sddrvcr0
); /* Enlarge drivability of LPDQS0-3, LPCLK */
73 writel(0x30000000, &sbsc
->sdwcr2
);
75 writel(readl(&sbsc
->sdpcr
) | 0x80, &sbsc
->sdpcr
);
76 cmp_loop(&sbsc
->sdpcr
, 0x80, 0x80);
78 writel(0x00002710, &sbsc
->sdgencnt
);
79 cmp_loop(&sbsc
->sdgencnt
, 0xffffffff, 0x0);
81 writel(0x0000003f, &sbsc
->sdmracr0
);
83 writel(0x000001f4, &sbsc
->sdgencnt
);
84 cmp_loop(&sbsc
->sdgencnt
, 0xffffffff, 0x0);
86 writel(0x0000ff0a, &sbsc
->sdmracr0
);
87 if (sbsc
== (struct sh73a0_sbsc
*)SBSC1_BASE
)
92 writel(0x00000032, &sbsc
->sdgencnt
);
93 cmp_loop(&sbsc
->sdgencnt
, 0xffffffff, 0x0);
95 if (sbsc
== (struct sh73a0_sbsc
*)SBSC1_BASE
) {
96 writel(0x00002201, &sbsc
->sdmracr0
);
98 writel(0x00000402, &sbsc
->sdmracr0
);
100 writel(0x00000203, &sbsc
->sdmracr0
); /* MR3 register DS=2 */
101 writel(0x0, SDMRA1A
);
102 writel(0x0, SDMRA2A
);
104 writel(0x00002201, &sbsc
->sdmracr0
);
105 writel(0x0, SDMRA1B
);
106 writel(0x00000402, &sbsc
->sdmracr0
);
107 writel(0x0, SDMRA1B
);
108 writel(0x00000203, &sbsc
->sdmracr0
); /* MR3 register DS=2 */
109 writel(0x0, SDMRA1B
);
110 writel(0x0, SDMRA2B
);
113 writel(0x88800004, &sbsc
->sdmrtmpcr
);
114 writel(0x00000004, &sbsc
->sdmrtmpmsk
);
115 writel(0xa55a0032, &sbsc
->rtcor
);
116 writel(0xa55a000c, &sbsc
->rtcorh
);
117 writel(0xa55a2048, &sbsc
->rtcsr
);
118 writel(readl(&sbsc
->sdcr0
)|0x800, &sbsc
->sdcr0
);
119 writel(readl(&sbsc
->sdcr1
)|0x400, &sbsc
->sdcr1
);
120 writel(0xfff20000, &sbsc
->zqccr
);
123 if (sbsc
== (struct sh73a0_sbsc
*)SBSC2_BASE
) {
124 writel(readl(&sbsc
->sdpdcr0
)|0x00030000, &sbsc
->sdpdcr0
);
125 writel(0xa5390000, &sbsc
->dphycnt1
);
126 writel(0x00001200, &sbsc
->dphycnt0
);
127 writel(0x07ce0000, &sbsc
->dphycnt1
);
128 writel(0x00001247, &sbsc
->dphycnt0
);
129 cmp_loop(&sbsc
->dphycnt2
, 0xffffffff, 0x07ce0000);
130 writel(readl(&sbsc
->sdpdcr0
) & 0xfffcffff, &sbsc
->sdpdcr0
);
136 struct sh73a0_rwdt
*rwdt
= (struct sh73a0_rwdt
*)RWDT_BASE
;
137 struct sh73a0_sbsc_cpg
*cpg
= (struct sh73a0_sbsc_cpg
*)CPG_BASE
;
138 struct sh73a0_sbsc_cpg_srcr
*cpg_srcr
=
139 (struct sh73a0_sbsc_cpg_srcr
*)CPG_SRCR_BASE
;
140 struct sh73a0_sbsc
*sbsc1
= (struct sh73a0_sbsc
*)SBSC1_BASE
;
141 struct sh73a0_sbsc
*sbsc2
= (struct sh73a0_sbsc
*)SBSC2_BASE
;
142 struct sh73a0_hpb
*hpb
= (struct sh73a0_hpb
*)HPB_BASE
;
143 struct sh73a0_hpb_bscr
*hpb_bscr
=
144 (struct sh73a0_hpb_bscr
*)HPBSCR_BASE
;
147 writew(0xA507, &rwdt
->rwtcsra0
);
149 /* Secure control register Init */
150 #define LIFEC_SEC_SRC_BIT (1 << 15)
151 writel(readl(LIFEC_SEC_SRC
) & ~LIFEC_SEC_SRC_BIT
, LIFEC_SEC_SRC
);
153 clrbits_le32(&cpg
->smstpcr3
, (1 << 15));
154 clrbits_le32(&cpg_srcr
->srcr3
, (1 << 15));
155 clrbits_le32(&cpg
->smstpcr2
, (1 << 18));
156 clrbits_le32(&cpg_srcr
->srcr2
, (1 << 18));
157 writel(0x0, &cpg
->pllecr
);
159 cmp_loop(&cpg
->pllecr
, 0x00000F00, 0x0);
160 cmp_loop(&cpg
->frqcrb
, 0x80000000, 0x0);
162 writel(0x2D000000, &cpg
->pll0cr
);
163 writel(0x17100000, &cpg
->pll1cr
);
164 writel(0x96235880, &cpg
->frqcrb
);
165 cmp_loop(&cpg
->frqcrb
, 0x80000000, 0x0);
167 writel(0xB, &cpg
->flckcr
);
168 clrbits_le32(&cpg
->smstpcr0
, (1 << 1));
170 clrbits_le32(&cpg_srcr
->srcr0
, (1 << 1));
171 writel(0x0514, &hpb_bscr
->smgpiotime
);
172 writel(0x0514, &hpb_bscr
->smcmt2time
);
173 writel(0x0514, &hpb_bscr
->smcpgtime
);
174 writel(0x0514, &hpb_bscr
->smsysctime
);
176 writel(0x00092000, &cpg
->dvfscr4
);
177 writel(0x000000DC, &cpg
->dvfscr5
);
178 writel(0x0, &cpg
->pllecr
);
179 cmp_loop(&cpg
->pllecr
, 0x00000F00, 0x0);
182 writel(0x0012453C, &cpg
->frqcra
);
183 writel(0x80431350, &cpg
->frqcrb
); /* ETM TRCLK 78MHz */
184 cmp_loop(&cpg
->frqcrb
, 0x80000000, 0x0);
185 writel(0x00000B0B, &cpg
->frqcrd
);
186 cmp_loop(&cpg
->frqcrd
, 0x80000000, 0x0);
189 writel(0x00000003, PCLKCR
);
190 writel(0x0000012F, &cpg
->vclkcr1
);
191 writel(0x00000119, &cpg
->vclkcr2
);
192 writel(0x00000119, &cpg
->vclkcr3
);
193 writel(0x00000002, &cpg
->zbckcr
);
194 writel(0x00000005, &cpg
->flckcr
);
195 writel(0x00000080, &cpg
->sd0ckcr
);
196 writel(0x00000080, &cpg
->sd1ckcr
);
197 writel(0x00000080, &cpg
->sd2ckcr
);
198 writel(0x0000003F, &cpg
->fsiackcr
);
199 writel(0x0000003F, &cpg
->fsibckcr
);
200 writel(0x00000080, &cpg
->subckcr
);
201 writel(0x0000000B, &cpg
->spuackcr
);
202 writel(0x0000000B, &cpg
->spuvckcr
);
203 writel(0x0000013F, &cpg
->msuckcr
);
204 writel(0x00000080, &cpg
->hsickcr
);
205 writel(0x0000003F, &cpg
->mfck1cr
);
206 writel(0x0000003F, &cpg
->mfck2cr
);
207 writel(0x00000107, &cpg
->dsitckcr
);
208 writel(0x00000313, &cpg
->dsi0pckcr
);
209 writel(0x0000130D, &cpg
->dsi1pckcr
);
210 writel(0x2A800E0E, &cpg
->dsi0phycr
);
211 writel(0x1E000000, &cpg
->pll0cr
);
212 writel(0x2D000000, &cpg
->pll0cr
);
213 writel(0x17100000, &cpg
->pll1cr
);
214 writel(0x27000080, &cpg
->pll2cr
);
215 writel(0x1D000000, &cpg
->pll3cr
);
216 writel(0x00080000, &cpg
->pll0stpcr
);
217 writel(0x000120C0, &cpg
->pll1stpcr
);
218 writel(0x00012000, &cpg
->pll2stpcr
);
219 writel(0x00000030, &cpg
->pll3stpcr
);
221 writel(0x0000000B, &cpg
->pllecr
);
222 cmp_loop(&cpg
->pllecr
, 0x00000B00, 0x00000B00);
224 writel(0x000120F0, &cpg
->dvfscr3
);
225 writel(0x00000020, &cpg
->mpmode
);
226 writel(0x0000028A, &cpg
->vrefcr
);
227 writel(0xE4628087, &cpg
->rmstpcr0
);
228 writel(0xFFFFFFFF, &cpg
->rmstpcr1
);
229 writel(0x53FFFFFF, &cpg
->rmstpcr2
);
230 writel(0xFFFFFFFF, &cpg
->rmstpcr3
);
231 writel(0x00800D3D, &cpg
->rmstpcr4
);
232 writel(0xFFFFF3FF, &cpg
->rmstpcr5
);
233 writel(0x00000000, &cpg
->smstpcr2
);
234 writel(0x00040000, &cpg_srcr
->srcr2
);
236 clrbits_le32(&cpg
->pllecr
, (1 << 3));
237 cmp_loop(&cpg
->pllecr
, 0x00000800, 0x0);
239 writel(0x00000001, &hpb
->hpbctrl6
);
240 cmp_loop(&hpb
->hpbctrl6
, 0x1, 0x1);
242 writel(0x00001414, &cpg
->frqcrd
);
243 cmp_loop(&cpg
->frqcrd
, 0x80000000, 0x0);
245 writel(0x1d000000, &cpg
->pll3cr
);
246 setbits_le32(&cpg
->pllecr
, (1 << 3));
247 cmp_loop(&cpg
->pllecr
, 0x800, 0x800);
255 writel(0x00000b0b, &cpg
->frqcrd
);
256 cmp_loop(&cpg
->frqcrd
, 0x80000000, 0x0);
257 writel(0xfffffffc, &cpg
->cpgxxcs4
);
260 int board_early_init_f(void)
262 struct sh73a0_sbsc_cpg
*cpg
= (struct sh73a0_sbsc_cpg
*)CPG_BASE
;
263 struct sh73a0_bsc
*bsc
= (struct sh73a0_bsc
*)BSC_BASE
;
264 struct sh73a0_sbsc_cpg_srcr
*cpg_srcr
=
265 (struct sh73a0_sbsc_cpg_srcr
*)CPG_SRCR_BASE
;
267 writel(CS0BCR_D
, &bsc
->cs0bcr
);
268 writel(CS4BCR_D
, &bsc
->cs4bcr
);
269 writel(CS0WCR_D
, &bsc
->cs0wcr
);
270 writel(CS4WCR_D
, &bsc
->cs4wcr
);
272 clrsetbits_le32(&bsc
->cmncr
, ~CMNCR_BROMMD
, CMNCR_BROMMD
);
274 clrbits_le32(&cpg
->smstpcr1
, (SMSTPCR1_CMT0
|SMSTPCR1_I2C0
));
275 clrbits_le32(&cpg_srcr
->srcr1
, (SMSTPCR1_CMT0
|SMSTPCR1_I2C0
));
276 clrbits_le32(&cpg
->smstpcr3
, (SMSTPCR3_USB
|SMSTPCR3_I2C1
));
277 clrbits_le32(&cpg_srcr
->srcr3
, (SMSTPCR3_USB
|SMSTPCR3_I2C1
));
278 writel(VCLKCR1_D
, &cpg
->vclkcr1
);
280 /* Setup SCIF4 / workaround */
281 writeb(0x12, PORT32CR
);
282 writeb(0x22, PORT33CR
);
283 writeb(0x12, PORT34CR
);
284 writeb(0x22, PORT35CR
);
289 void adjust_core_voltage(void)
295 i2c_write(0x40, 3, 1, &data
, 1);
300 adjust_core_voltage();
301 sh73a0_pinmux_init();
304 gpio_request(GPIO_FN_SCIFA4_TXD
, NULL
);
305 gpio_request(GPIO_FN_SCIFA4_RXD
, NULL
);
306 gpio_request(GPIO_FN_SCIFA4_RTS_
, NULL
);
307 gpio_request(GPIO_FN_SCIFA4_CTS_
, NULL
);
310 gpio_request(GPIO_PORT224
, NULL
);
311 gpio_direction_input(GPIO_PORT224
);
314 gpio_request(GPIO_FN_CS4_
, NULL
);
317 gpio_request(GPIO_FN_MMCCLK0
, NULL
);
318 gpio_request(GPIO_FN_MMCCMD0_PU
, NULL
);
319 gpio_request(GPIO_FN_MMCD0_0_PU
, NULL
);
320 gpio_request(GPIO_FN_MMCD0_1_PU
, NULL
);
321 gpio_request(GPIO_FN_MMCD0_2_PU
, NULL
);
322 gpio_request(GPIO_FN_MMCD0_3_PU
, NULL
);
323 gpio_request(GPIO_FN_MMCD0_4_PU
, NULL
);
324 gpio_request(GPIO_FN_MMCD0_5_PU
, NULL
);
325 gpio_request(GPIO_FN_MMCD0_6_PU
, NULL
);
326 gpio_request(GPIO_FN_MMCD0_7_PU
, NULL
);
329 gpio_request(GPIO_FN_SDHIWP0
, NULL
);
330 gpio_request(GPIO_FN_SDHICD0
, NULL
);
331 gpio_request(GPIO_FN_SDHICMD0
, NULL
);
332 gpio_request(GPIO_FN_SDHICLK0
, NULL
);
333 gpio_request(GPIO_FN_SDHID0_3
, NULL
);
334 gpio_request(GPIO_FN_SDHID0_2
, NULL
);
335 gpio_request(GPIO_FN_SDHID0_1
, NULL
);
336 gpio_request(GPIO_FN_SDHID0_0
, NULL
);
337 gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON
, NULL
);
338 gpio_request(GPIO_PORT15
, NULL
);
339 gpio_direction_output(GPIO_PORT15
, 1);
342 gpio_request(GPIO_FN_PORT237_I2C_SCL2
, NULL
);
343 gpio_request(GPIO_FN_PORT236_I2C_SDA2
, NULL
);
344 gpio_request(GPIO_FN_PORT27_I2C_SCL3
, NULL
);
345 gpio_request(GPIO_FN_PORT28_I2C_SDA3
, NULL
);
347 gd
->bd
->bi_boot_params
= (CONFIG_SYS_SDRAM_BASE
+ 0x100);
354 gd
->ram_size
= CONFIG_SYS_SDRAM_SIZE
;
358 int board_eth_init(bd_t
*bis
)
361 #ifdef CONFIG_SMC911X
362 ret
= smc911x_initialize(0, CONFIG_SMC911X_BASE
);
367 void reset_cpu(ulong addr
)
369 /* Soft Power On Reset */
370 writel((1 << 31), RESCNT2
);