board/korat/korat.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Larry Johnson, lrj@acm.org
   4  *
   5  * (C) Copyright 2006
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * (C) Copyright 2006
   9  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  10  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <asm/gpio.h>
  30 #include <asm/processor.h>
  31 #include <asm-ppc/io.h>
  32 #include <i2c.h>
  33 #include <ppc440.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];    /* info for FLASH chips    */
  38
  39 ulong flash_get_size(ulong base, int banknum);
  40
  41 int board_early_init_f(void)
  42 {
  43         u32 sdr0_pfc1, sdr0_pfc2;
  44         u32 reg;
  45         int eth;
  46
  47         mtdcr(ebccfga, xbcfg);
  48         mtdcr(ebccfgd, 0xb8400000);
  49
  50         /*--------------------------------------------------------------------
  51          * Setup the interrupt controller polarities, triggers, etc.
  52          *-------------------------------------------------------------------*/
  53         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  54         mtdcr(uic0er, 0x00000000);      /* disable all */
  55         mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
  56         mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
  57         mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
  58         mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
  59         mtdcr(uic0sr, 0xffffffff);      /* clear all */
  60
  61         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  62         mtdcr(uic1er, 0x00000000);      /* disable all */
  63         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
  64         mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
  65         mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
  66         mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
  67         mtdcr(uic1sr, 0xffffffff);      /* clear all */
  68
  69         mtdcr(uic2sr, 0xffffffff);      /* clear all */
  70         mtdcr(uic2er, 0x00000000);      /* disable all */
  71         mtdcr(uic2cr, 0x00000000);      /* all non-critical */
  72         mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
  73         mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
  74         mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
  75         mtdcr(uic2sr, 0xffffffff);      /* clear all */
  76
  77         /* take sim card reader and CF controller out of reset */
  78         out_8((u8 *) CFG_CPLD_BASE + 0x04, 0x80);
  79
  80         /* Configure the two Ethernet PHYs.  For each PHY, configure for fiber
  81          * if the SFP module is present, and for copper if it is not present.
  82          */
  83         for (eth = 0; eth < 2; ++eth) {
  84                 if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) {
  85                         /* SFP module not present: configure PHY for copper. */
  86                         /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
  87                         out_8((u8 *) CFG_CPLD_BASE + 0x06,
  88                               in_8((u8 *) CFG_CPLD_BASE + 0x06) |
  89                               0x06 << (4 * eth));
  90                 } else {
  91                         /* SFP module present: configure PHY for fiber and
  92                            enable output */
  93                         gpio_write_bit(CFG_GPIO_PHY0_FIBER_SEL + eth, 1);
  94                         gpio_write_bit(CFG_GPIO_SFP0_TX_EN_ + eth, 0);
  95                 }
  96         }
  97         /* enable Ethernet: set GPIO45 and GPIO46 to 1 */
  98         gpio_write_bit(CFG_GPIO_PHY0_EN, 1);
  99         gpio_write_bit(CFG_GPIO_PHY1_EN, 1);
 100
 101         /* select Ethernet pins */
 102         mfsdr(SDR0_PFC1, sdr0_pfc1);
 103         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
 104             SDR0_PFC1_SELECT_CONFIG_4;
 105         mfsdr(SDR0_PFC2, sdr0_pfc2);
 106         sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
 107             SDR0_PFC2_SELECT_CONFIG_4;
 108         mtsdr(SDR0_PFC2, sdr0_pfc2);
 109         mtsdr(SDR0_PFC1, sdr0_pfc1);
 110
 111         /* PCI arbiter enabled */
 112         mfsdr(sdr_pci0, reg);
 113         mtsdr(sdr_pci0, 0x80000000 | reg);
 114
 115         return 0;
 116 }
 117
 118 static int man_data_read(unsigned int addr)
 119 {
 120         /*
 121          * Read an octet of data from address "addr" in the manufacturer's
 122          * information serial EEPROM, or -1 on error.
 123          */
 124         u8 data[2];
 125
 126         if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
 127             0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
 128                 debug("man_data_read(0x%02X) failed\n", addr);
 129                 return -1;
 130         }
 131         debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
 132         return data[0];
 133 }
 134
 135 static unsigned int man_data_field_addr(unsigned int const field)
 136 {
 137         /*
 138          * The manufacturer's information serial EEPROM contains a sequence of
 139          * zero-delimited fields.  Return the starting address of field "field",
 140          * or 0 on error.
 141          */
 142         unsigned addr, i;
 143
 144         if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
 145                 /* Only format "A" is currently supported */
 146                 return 0;
 147
 148         for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
 149                 if ('\0' == man_data_read(addr))
 150                         ++i;
 151         }
 152         return (addr < 256) ? addr : 0;
 153 }
 154
 155 static char *man_data_read_field(char s[], unsigned const field,
 156                                  unsigned const length)
 157 {
 158         /*
 159          * Place the null-terminated contents of field "field" of length
 160          * "length" from the manufacturer's information serial EEPROM into
 161          * string "s[length + 1]" and return a pointer to s, or return 0 on
 162          * error. In either case the original contents of s[] is not preserved.
 163          */
 164         unsigned addr, i;
 165
 166         addr = man_data_field_addr(field);
 167         if (0 == addr || addr + length >= 255)
 168                 return 0;
 169
 170         for (i = 0; i < length; ++i) {
 171                 int const c = man_data_read(addr++);
 172
 173                 if (c <= 0)
 174                         return 0;
 175
 176                 s[i] = (char)c;
 177         }
 178         if (0 != man_data_read(addr))
 179                 return 0;
 180
 181         s[i] = '\0';
 182         return s;
 183 }
 184
 185 static void set_serial_number(void)
 186 {
 187         /*
 188          * If the environmental variable "serial#" is not set, try to set it
 189          * from the manufacturer's information serial EEPROM.
 190          */
 191         char s[MAN_SERIAL_NO_LENGTH + 1];
 192
 193         if (0 == getenv("serial#") &&
 194             0 != man_data_read_field(s, MAN_SERIAL_NO_FIELD,
 195                                      MAN_SERIAL_NO_LENGTH))
 196                 setenv("serial#", s);
 197 }
 198
 199 static void set_mac_addresses(void)
 200 {
 201         /*
 202          * If the environmental variables "ethaddr" and/or "eth1addr" are not
 203          * set, try to set them from the manufacturer's information serial
 204          * EEPROM.
 205          */
 206         char s[MAN_MAC_ADDR_LENGTH + 1];
 207
 208         if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
 209                 return;
 210
 211         if (0 == man_data_read_field(s, MAN_MAC_ADDR_FIELD,
 212                                      MAN_MAC_ADDR_LENGTH))
 213                 return;
 214
 215         if (0 == getenv("ethaddr"))
 216                 setenv("ethaddr", s);
 217
 218         if (0 == getenv("eth1addr")) {
 219                 ++s[MAN_MAC_ADDR_LENGTH - 1];
 220                 setenv("eth1addr", s);
 221         }
 222 }
 223
 224 /*---------------------------------------------------------------------------+
 225   | misc_init_r.
 226   +---------------------------------------------------------------------------*/
 227 int misc_init_r(void)
 228 {
 229         uint pbcr;
 230         int size_val = 0;
 231         u32 reg;
 232         unsigned long usb2d0cr = 0;
 233         unsigned long usb2phy0cr, usb2h0cr = 0;
 234         unsigned long sdr0_pfc1;
 235         char *act = getenv("usbact");
 236
 237         /*
 238          * FLASH stuff...
 239          */
 240
 241         /* Re-do sizing to get full correct info */
 242
 243         /* adjust flash start and offset */
 244         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 245         gd->bd->bi_flashoffset = 0;
 246
 247         mtdcr(ebccfga, pb0cr);
 248         pbcr = mfdcr(ebccfgd);
 249         switch (gd->bd->bi_flashsize) {
 250         case 1 << 20:
 251                 size_val = 0;
 252                 break;
 253         case 2 << 20:
 254                 size_val = 1;
 255                 break;
 256         case 4 << 20:
 257                 size_val = 2;
 258                 break;
 259         case 8 << 20:
 260                 size_val = 3;
 261                 break;
 262         case 16 << 20:
 263                 size_val = 4;
 264                 break;
 265         case 32 << 20:
 266                 size_val = 5;
 267                 break;
 268         case 64 << 20:
 269                 size_val = 6;
 270                 break;
 271         case 128 << 20:
 272                 size_val = 7;
 273                 break;
 274         }
 275         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 276         mtdcr(ebccfga, pb0cr);
 277         mtdcr(ebccfgd, pbcr);
 278
 279         /*
 280          * Re-check to get correct base address
 281          */
 282         flash_get_size(gd->bd->bi_flashstart, 0);
 283
 284         /* Monitor protection ON by default */
 285         (void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff,
 286                             &flash_info[0]);
 287
 288         /* Env protection ON by default */
 289         (void)flash_protect(FLAG_PROTECT_SET,
 290                             CFG_ENV_ADDR_REDUND,
 291                             CFG_ENV_ADDR_REDUND + 2 * CFG_ENV_SECT_SIZE - 1,
 292                             &flash_info[0]);
 293
 294         /*
 295          * USB suff...
 296          */
 297         if (act == NULL || strcmp(act, "hostdev") == 0) {
 298                 /* SDR Setting */
 299                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 300                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 301                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 302                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 303
 304                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
 305                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0 */
 306                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
 307                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;    /*1 */
 308                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
 309                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */
 310                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
 311                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;  /*1 */
 312                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
 313                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;  /*1 */
 314
 315                 /* An 8-bit/60MHz interface is the only possible alternative
 316                    when connecting the Device to the PHY */
 317                 usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
 318                 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;  /*1 */
 319
 320                 /* To enable the USB 2.0 Device function through the UTMI interface */
 321                 usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 322                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;  /*1 */
 323
 324                 sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK;
 325                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;        /*0 */
 326
 327                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 328                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 329                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 330                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 331
 332                 /*clear resets */
 333                 udelay(1000);
 334                 mtsdr(SDR0_SRST1, 0x00000000);
 335                 udelay(1000);
 336                 mtsdr(SDR0_SRST0, 0x00000000);
 337
 338                 printf("USB:   Host(int phy) Device(ext phy)\n");
 339
 340         } else if (strcmp(act, "dev") == 0) {
 341                 /*-------------------PATCH-------------------------------*/
 342                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 343
 344                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
 345                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0 */
 346                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
 347                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */
 348                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
 349                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;  /*1 */
 350                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
 351                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;  /*1 */
 352                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 353
 354                 udelay(1000);
 355                 mtsdr(SDR0_SRST1, 0x672c6000);
 356
 357                 udelay(1000);
 358                 mtsdr(SDR0_SRST0, 0x00000080);
 359
 360                 udelay(1000);
 361                 mtsdr(SDR0_SRST1, 0x60206000);
 362
 363                 *(unsigned int *)(0xe0000350) = 0x00000001;
 364
 365                 udelay(1000);
 366                 mtsdr(SDR0_SRST1, 0x60306000);
 367                 /*-------------------PATCH-------------------------------*/
 368
 369                 /* SDR Setting */
 370                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 371                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 372                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 373                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 374
 375                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
 376                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;       /*0 */
 377                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
 378                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;     /*0 */
 379                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
 380                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;  /*1 */
 381                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
 382                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;   /*0 */
 383                 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
 384                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;   /*0 */
 385
 386                 usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
 387                 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;   /*0 */
 388
 389                 usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 390                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;      /*0 */
 391
 392                 sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK;
 393                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;        /*1 */
 394
 395                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 396                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 397                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 398                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 399
 400                 /*clear resets */
 401                 udelay(1000);
 402                 mtsdr(SDR0_SRST1, 0x00000000);
 403                 udelay(1000);
 404                 mtsdr(SDR0_SRST0, 0x00000000);
 405
 406                 printf("USB:   Device(int phy)\n");
 407         }
 408
 409         mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
 410         reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
 411         mtsdr(SDR0_SRST1, reg);
 412
 413         /*
 414          * Clear PLB4A0_ACR[WRP]
 415          * This fix will make the MAL burst disabling patch for the Linux
 416          * EMAC driver obsolete.
 417          */
 418         reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
 419         mtdcr(plb4_acr, reg);
 420
 421         set_serial_number();
 422         set_mac_addresses();
 423         return 0;
 424 }
 425
 426 int checkboard(void)
 427 {
 428         char const *const s = getenv("serial#");
 429         u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0);
 430
 431         printf("Board: Korat, Rev. %X", rev);
 432         if (s != NULL)
 433                 printf(", serial# %s", s);
 434
 435         printf(", Ethernet PHY 0: ");
 436         if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL))
 437                 printf("fiber");
 438         else
 439                 printf("copper");
 440
 441         printf(", PHY 1: ");
 442         if (gpio_read_out_bit(CFG_GPIO_PHY1_FIBER_SEL))
 443                 printf("fiber");
 444         else
 445                 printf("copper");
 446
 447         printf(".\n");
 448         return (0);
 449 }
 450
 451 #if defined(CFG_DRAM_TEST)
 452 int testdram(void)
 453 {
 454         unsigned long *mem = (unsigned long *)0;
 455         const unsigned long kend = (1024 / sizeof(unsigned long));
 456         unsigned long k, n;
 457
 458         mtmsr(0);
 459
 460         /* TODO: find correct size of SDRAM */
 461         for (k = 0; k < CFG_MBYTES_SDRAM;
 462              ++k, mem += (1024 / sizeof(unsigned long))) {
 463                 if ((k & 1023) == 0)
 464                         printf("%3d MB\r", k / 1024);
 465
 466                 memset(mem, 0xaaaaaaaa, 1024);
 467                 for (n = 0; n < kend; ++n) {
 468                         if (mem[n] != 0xaaaaaaaa) {
 469                                 printf("SDRAM test fails at: %08x\n",
 470                                        (uint) & mem[n]);
 471                                 return 1;
 472                         }
 473                 }
 474
 475                 memset(mem, 0x55555555, 1024);
 476                 for (n = 0; n < kend; ++n) {
 477                         if (mem[n] != 0x55555555) {
 478                                 printf("SDRAM test fails at: %08x\n",
 479                                        (uint) & mem[n]);
 480                                 return 1;
 481                         }
 482                 }
 483         }
 484         printf("SDRAM test passes\n");
 485         return 0;
 486 }
 487 #endif /* defined(CFG_DRAM_TEST) */
 488
 489 /*************************************************************************
 490  *  pci_pre_init
 491  *
 492  *  This routine is called just prior to registering the hose and gives
 493  *  the board the opportunity to check things. Returning a value of zero
 494  *  indicates that things are bad & PCI initialization should be aborted.
 495  *
 496  *      Different boards may wish to customize the pci controller structure
 497  *      (add regions, override default access routines, etc) or perform
 498  *      certain pre-initialization actions.
 499  *
 500  ************************************************************************/
 501 #if defined(CONFIG_PCI)
 502 int pci_pre_init(struct pci_controller *hose)
 503 {
 504         unsigned long addr;
 505
 506         /*-------------------------------------------------------------------------+
 507           | Set priority for all PLB3 devices to 0.
 508           | Set PLB3 arbiter to fair mode.
 509           +-------------------------------------------------------------------------*/
 510         mfsdr(sdr_amp1, addr);
 511         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 512         addr = mfdcr(plb3_acr);
 513         mtdcr(plb3_acr, addr | 0x80000000);
 514
 515         /*-------------------------------------------------------------------------+
 516           | Set priority for all PLB4 devices to 0.
 517           +-------------------------------------------------------------------------*/
 518         mfsdr(sdr_amp0, addr);
 519         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 520         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 521         mtdcr(plb4_acr, addr);
 522
 523         /*-------------------------------------------------------------------------+
 524           | Set Nebula PLB4 arbiter to fair mode.
 525           +-------------------------------------------------------------------------*/
 526         /* Segment0 */
 527         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 528         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 529         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 530         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 531         mtdcr(plb0_acr, addr);
 532
 533         /* Segment1 */
 534         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 535         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 536         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 537         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 538         mtdcr(plb1_acr, addr);
 539
 540         return 1;
 541 }
 542 #endif /* defined(CONFIG_PCI) */
 543
 544 /*************************************************************************
 545  *  pci_target_init
 546  *
 547  *      The bootstrap configuration provides default settings for the pci
 548  *      inbound map (PIM). But the bootstrap config choices are limited and
 549  *      may not be sufficient for a given board.
 550  *
 551  ************************************************************************/
 552 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 553 void pci_target_init(struct pci_controller *hose)
 554 {
 555         /*--------------------------------------------------------------------------+
 556          * Set up Direct MMIO registers
 557          *--------------------------------------------------------------------------*/
 558         /*--------------------------------------------------------------------------+
 559           | PowerPC440EPX PCI Master configuration.
 560           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 561           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 562           |   Use byte reversed out routines to handle endianess.
 563           | Make this region non-prefetchable.
 564           +--------------------------------------------------------------------------*/
 565         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 566         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 567         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 568         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 569         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 570
 571         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 572         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 573         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 574         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 575         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 576
 577         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 578         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 579         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 580         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 581
 582         /*--------------------------------------------------------------------------+
 583          * Set up Configuration registers
 584          *--------------------------------------------------------------------------*/
 585
 586         /* Program the board's subsystem id/vendor id */
 587         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 588                               CFG_PCI_SUBSYS_VENDORID);
 589         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 590
 591         /* Configure command register as bus master */
 592         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 593
 594         /* 240nS PCI clock */
 595         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 596
 597         /* No error reporting */
 598         pci_write_config_word(0, PCI_ERREN, 0);
 599
 600         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 601
 602         /*--------------------------------------------------------------------------+
 603          * Set up Configuration registers for on-board NEC uPD720101 USB controller
 604          *--------------------------------------------------------------------------*/
 605         pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
 606 }
 607 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 608
 609 /*************************************************************************
 610  *  pci_master_init
 611  *
 612  ************************************************************************/
 613 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 614 void pci_master_init(struct pci_controller *hose)
 615 {
 616         unsigned short temp_short;
 617
 618         /*--------------------------------------------------------------------------+
 619           | Write the PowerPC440 EP PCI Configuration regs.
 620           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 621           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 622           +--------------------------------------------------------------------------*/
 623         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 624         pci_write_config_word(0, PCI_COMMAND,
 625                               temp_short | PCI_COMMAND_MASTER |
 626                               PCI_COMMAND_MEMORY);
 627 }
 628 #endif
 629
 630 /*************************************************************************
 631  *  is_pci_host
 632  *
 633  *      This routine is called to determine if a pci scan should be
 634  *      performed. With various hardware environments (especially cPCI and
 635  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 636  *      bit in the strap register, or generic host/adapter assumptions.
 637  *
 638  *      Rather than hard-code a bad assumption in the general 440 code, the
 639  *      440 pci code requires the board to decide at runtime.
 640  *
 641  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 642  *
 643  *
 644  ************************************************************************/
 645 #if defined(CONFIG_PCI)
 646 int is_pci_host(struct pci_controller *hose)
 647 {
 648         /* Korat is always configured as host. */
 649         return (1);
 650 }
 651 #endif
 652
 653 #if defined(CONFIG_POST)
 654 /*
 655  * Returns 1 if keys pressed to start the power-on long-running tests
 656  * Called from board_init_f().
 657  */
 658 int post_hotkeys_pressed(void)
 659 {
 660         return 0;               /* No hotkeys supported */
 661 }
 662 #endif