board/kup4k/s1d13706.h

   1 /*---------------------------------------------------------------------------- */
   2 /* */
   3 /*  File generated by S1D13706CFG.EXE */
   4 /* */
   5 /*  Copyright (c) 2000,2001 Epson Research and Development, Inc. */
   6 /*  All rights reserved. */
   7 /* */
   8 /*---------------------------------------------------------------------------- */
   9
  10 /* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */
  11
  12 #define S1D_DISPLAY_WIDTH           320
  13 #define S1D_DISPLAY_HEIGHT          240
  14 #define S1D_DISPLAY_BPP             8
  15 #define S1D_DISPLAY_SCANLINE_BYTES  320
  16 #define S1D_PHYSICAL_VMEM_ADDR      0x800A0000L
  17 #define S1D_PHYSICAL_VMEM_SIZE      0x14000L
  18 #define S1D_PHYSICAL_REG_ADDR       0x80080000L
  19 #define S1D_PHYSICAL_REG_SIZE       0x100
  20 #define S1D_DISPLAY_PCLK            6250
  21 #define S1D_PALETTE_SIZE            256
  22 #define S1D_REGDELAYOFF             0xFFFE
  23 #define S1D_REGDELAYON              0xFFFF
  24
  25 #define S1D_WRITE_PALETTE(p,i,r,g,b)  \
  26 {  \
  27     ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4);  \
  28     ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4);  \
  29     ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4);  \
  30     ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);  \
  31 }
  32
  33 #define S1D_READ_PALETTE(p,i,r,g,b)  \
  34 {  \
  35     ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);  \
  36     r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)];  \
  37     g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)];  \
  38     b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)];  \
  39 }
  40
  41 typedef unsigned short S1D_INDEX;
  42 typedef unsigned char  S1D_VALUE;
  43
  44
  45 typedef struct
  46 {
  47     S1D_INDEX Index;
  48     S1D_VALUE Value;
  49 } S1D_REGS;
  50
  51 static S1D_REGS aS1DRegs[] =
  52 {
  53         {0x04,0x10},    /* BUSCLK MEMCLK Config Register */
  54 #if 0
  55         {0x05,0x32},    /* PCLK Config  Register  */
  56 #endif
  57         {0x10,0xD0},    /* PANEL Type Register */
  58         {0x11,0x00},    /* MOD Rate Register */
  59 #if 0
  60         {0x12,0x34},    /* Horizontal Total Register */
  61 #endif
  62         {0x14,0x27},    /* Horizontal Display Period Register */
  63         {0x16,0x00},    /* Horizontal Display Period Start Pos Register 0 */
  64         {0x17,0x00},    /* Horizontal Display Period Start Pos Register 1 */
  65         {0x18,0xF0},    /* Vertical Total Register 0  */
  66         {0x19,0x00},    /* Vertical Total Register 1 */
  67         {0x1C,0xEF},    /* Vertical Display Period Register 0 */
  68         {0x1D,0x00},    /* Vertical Display Period Register 1 */
  69         {0x1E,0x00},    /* Vertical Display Period Start Pos Register 0 */
  70         {0x1F,0x00},    /* Vertical Display Period Start Pos Register 1 */
  71         {0x20,0x87},    /* Horizontal Sync Pulse Width Register */
  72         {0x22,0x00},    /* Horizontal Sync Pulse Start Pos Register 0 */
  73         {0x23,0x00},    /* Horizontal Sync Pulse Start Pos Register 1 */
  74         {0x24,0x80},    /* Vertical Sync Pulse Width Register */
  75         {0x26,0x01},    /* Vertical Sync Pulse Start Pos Register 0 */
  76         {0x27,0x00},    /* Vertical Sync Pulse Start Pos Register 1 */
  77         {0x70,0x83},    /* Display Mode Register */
  78         {0x71,0x00},    /* Special Effects Register */
  79         {0x74,0x00},    /* Main Window Display Start Address Register 0 */
  80         {0x75,0x00},    /* Main Window Display Start Address Register 1 */
  81         {0x76,0x00},    /* Main Window Display Start Address Register 2 */
  82         {0x78,0x50},    /* Main Window Address Offset Register 0 */
  83         {0x79,0x00},    /* Main Window Address Offset Register 1 */
  84         {0x7C,0x00},    /* Sub Window Display Start Address Register 0 */
  85         {0x7D,0x00},    /* Sub Window Display Start Address Register 1 */
  86         {0x7E,0x00},    /* Sub Window Display Start Address Register 2 */
  87         {0x80,0x50},    /* Sub Window Address Offset Register 0 */
  88         {0x81,0x00},    /* Sub Window Address Offset Register 1 */
  89         {0x84,0x00},    /* Sub Window X Start Pos Register 0 */
  90         {0x85,0x00},    /* Sub Window X Start Pos Register 1 */
  91         {0x88,0x00},    /* Sub Window Y Start Pos Register 0 */
  92         {0x89,0x00},    /* Sub Window Y Start Pos Register 1 */
  93         {0x8C,0x4F},    /* Sub Window X End Pos Register 0 */
  94         {0x8D,0x00},    /* Sub Window X End Pos Register 1 */
  95         {0x90,0xEF},    /* Sub Window Y End Pos Register 0 */
  96         {0x91,0x00},    /* Sub Window Y End Pos Register 1 */
  97         {0xA0,0x00},    /* Power Save Config Register */
  98         {0xA1,0x00},    /* CPU Access Control Register */
  99         {0xA2,0x00},    /* Software Reset Register */
 100         {0xA3,0x00},    /* BIG Endian Support Register */
 101         {0xA4,0x00},    /* Scratch Pad Register 0 */
 102         {0xA5,0x00},    /* Scratch Pad Register 1 */
 103         {0xA8,0x01},    /* GPIO Config Register 0 */
 104         {0xA9,0x80},    /* GPIO Config Register 1 */
 105         {0xAC,0x01},    /* GPIO Status Control Register 0 */
 106         {0xAD,0x00},    /* GPIO Status Control Register 1 */
 107         {0xB0,0x10},    /* PWM CV Clock Control Register */
 108         {0xB1,0x80},    /* PWM CV Clock Config Register */
 109         {0xB2,0x00},    /* CV Clock Burst Length Register */
 110         {0xB3,0xA0},    /* PWM Clock Duty Cycle Register */
 111         {0xAD,0x80},    /* reset seq */
 112         {0x70,0x03},    /*  */
 113 };