1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Wandboard
4 * Author: Tungyi Lin <tungyilin1127@gmail.com>
5 * Richard Hu <hakahu@gmail.com>
8 #include <asm/arch/clock.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/mx6-pins.h>
14 #include <asm/mach-imx/iomux-v3.h>
15 #include <asm/mach-imx/video.h>
17 #include <fsl_esdhc_imx.h>
18 #include <asm/arch/crm_regs.h>
20 #include <asm/arch/sys_proto.h>
23 #if defined(CONFIG_SPL_BUILD)
24 #include <asm/arch/mx6-ddr.h>
31 #define IMX6DQ_DRIVE_STRENGTH 0x30
32 #define IMX6SDL_DRIVE_STRENGTH 0x28
34 /* configure MX6Q/DUAL mmdc DDR io registers */
35 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs
= {
36 .dram_sdclk_0
= IMX6DQ_DRIVE_STRENGTH
,
37 .dram_sdclk_1
= IMX6DQ_DRIVE_STRENGTH
,
38 .dram_cas
= IMX6DQ_DRIVE_STRENGTH
,
39 .dram_ras
= IMX6DQ_DRIVE_STRENGTH
,
40 .dram_reset
= IMX6DQ_DRIVE_STRENGTH
,
41 .dram_sdcke0
= IMX6DQ_DRIVE_STRENGTH
,
42 .dram_sdcke1
= IMX6DQ_DRIVE_STRENGTH
,
43 .dram_sdba2
= 0x00000000,
44 .dram_sdodt0
= IMX6DQ_DRIVE_STRENGTH
,
45 .dram_sdodt1
= IMX6DQ_DRIVE_STRENGTH
,
46 .dram_sdqs0
= IMX6DQ_DRIVE_STRENGTH
,
47 .dram_sdqs1
= IMX6DQ_DRIVE_STRENGTH
,
48 .dram_sdqs2
= IMX6DQ_DRIVE_STRENGTH
,
49 .dram_sdqs3
= IMX6DQ_DRIVE_STRENGTH
,
50 .dram_sdqs4
= IMX6DQ_DRIVE_STRENGTH
,
51 .dram_sdqs5
= IMX6DQ_DRIVE_STRENGTH
,
52 .dram_sdqs6
= IMX6DQ_DRIVE_STRENGTH
,
53 .dram_sdqs7
= IMX6DQ_DRIVE_STRENGTH
,
54 .dram_dqm0
= IMX6DQ_DRIVE_STRENGTH
,
55 .dram_dqm1
= IMX6DQ_DRIVE_STRENGTH
,
56 .dram_dqm2
= IMX6DQ_DRIVE_STRENGTH
,
57 .dram_dqm3
= IMX6DQ_DRIVE_STRENGTH
,
58 .dram_dqm4
= IMX6DQ_DRIVE_STRENGTH
,
59 .dram_dqm5
= IMX6DQ_DRIVE_STRENGTH
,
60 .dram_dqm6
= IMX6DQ_DRIVE_STRENGTH
,
61 .dram_dqm7
= IMX6DQ_DRIVE_STRENGTH
,
64 /* configure MX6Q/DUAL mmdc GRP io registers */
65 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs
= {
66 .grp_ddr_type
= 0x000c0000,
67 .grp_ddrmode_ctl
= 0x00020000,
68 .grp_ddrpke
= 0x00000000,
69 .grp_addds
= IMX6DQ_DRIVE_STRENGTH
,
70 .grp_ctlds
= IMX6DQ_DRIVE_STRENGTH
,
71 .grp_ddrmode
= 0x00020000,
72 .grp_b0ds
= IMX6DQ_DRIVE_STRENGTH
,
73 .grp_b1ds
= IMX6DQ_DRIVE_STRENGTH
,
74 .grp_b2ds
= IMX6DQ_DRIVE_STRENGTH
,
75 .grp_b3ds
= IMX6DQ_DRIVE_STRENGTH
,
76 .grp_b4ds
= IMX6DQ_DRIVE_STRENGTH
,
77 .grp_b5ds
= IMX6DQ_DRIVE_STRENGTH
,
78 .grp_b6ds
= IMX6DQ_DRIVE_STRENGTH
,
79 .grp_b7ds
= IMX6DQ_DRIVE_STRENGTH
,
82 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
83 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs
= {
84 .dram_sdclk_0
= IMX6SDL_DRIVE_STRENGTH
,
85 .dram_sdclk_1
= IMX6SDL_DRIVE_STRENGTH
,
86 .dram_cas
= IMX6SDL_DRIVE_STRENGTH
,
87 .dram_ras
= IMX6SDL_DRIVE_STRENGTH
,
88 .dram_reset
= IMX6SDL_DRIVE_STRENGTH
,
89 .dram_sdcke0
= IMX6SDL_DRIVE_STRENGTH
,
90 .dram_sdcke1
= IMX6SDL_DRIVE_STRENGTH
,
91 .dram_sdba2
= 0x00000000,
92 .dram_sdodt0
= IMX6SDL_DRIVE_STRENGTH
,
93 .dram_sdodt1
= IMX6SDL_DRIVE_STRENGTH
,
94 .dram_sdqs0
= IMX6SDL_DRIVE_STRENGTH
,
95 .dram_sdqs1
= IMX6SDL_DRIVE_STRENGTH
,
96 .dram_sdqs2
= IMX6SDL_DRIVE_STRENGTH
,
97 .dram_sdqs3
= IMX6SDL_DRIVE_STRENGTH
,
98 .dram_sdqs4
= IMX6SDL_DRIVE_STRENGTH
,
99 .dram_sdqs5
= IMX6SDL_DRIVE_STRENGTH
,
100 .dram_sdqs6
= IMX6SDL_DRIVE_STRENGTH
,
101 .dram_sdqs7
= IMX6SDL_DRIVE_STRENGTH
,
102 .dram_dqm0
= IMX6SDL_DRIVE_STRENGTH
,
103 .dram_dqm1
= IMX6SDL_DRIVE_STRENGTH
,
104 .dram_dqm2
= IMX6SDL_DRIVE_STRENGTH
,
105 .dram_dqm3
= IMX6SDL_DRIVE_STRENGTH
,
106 .dram_dqm4
= IMX6SDL_DRIVE_STRENGTH
,
107 .dram_dqm5
= IMX6SDL_DRIVE_STRENGTH
,
108 .dram_dqm6
= IMX6SDL_DRIVE_STRENGTH
,
109 .dram_dqm7
= IMX6SDL_DRIVE_STRENGTH
,
112 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
113 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
114 .grp_ddr_type
= 0x000c0000,
115 .grp_ddrmode_ctl
= 0x00020000,
116 .grp_ddrpke
= 0x00000000,
117 .grp_addds
= IMX6SDL_DRIVE_STRENGTH
,
118 .grp_ctlds
= IMX6SDL_DRIVE_STRENGTH
,
119 .grp_ddrmode
= 0x00020000,
120 .grp_b0ds
= IMX6SDL_DRIVE_STRENGTH
,
121 .grp_b1ds
= IMX6SDL_DRIVE_STRENGTH
,
122 .grp_b2ds
= IMX6SDL_DRIVE_STRENGTH
,
123 .grp_b3ds
= IMX6SDL_DRIVE_STRENGTH
,
124 .grp_b4ds
= IMX6SDL_DRIVE_STRENGTH
,
125 .grp_b5ds
= IMX6SDL_DRIVE_STRENGTH
,
126 .grp_b6ds
= IMX6SDL_DRIVE_STRENGTH
,
127 .grp_b7ds
= IMX6SDL_DRIVE_STRENGTH
,
131 static struct mx6_ddr3_cfg h5t04g63afr
= {
145 static struct mx6_ddr3_cfg h5tq2g63dfr
= {
158 static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib
= {
159 .p0_mpwldectrl0
= 0x001f001f,
160 .p0_mpwldectrl1
= 0x001f001f,
161 .p1_mpwldectrl0
= 0x001f001f,
162 .p1_mpwldectrl1
= 0x001f001f,
163 .p0_mpdgctrl0
= 0x4301030d,
164 .p0_mpdgctrl1
= 0x03020277,
165 .p1_mpdgctrl0
= 0x4300030a,
166 .p1_mpdgctrl1
= 0x02780248,
167 .p0_mprddlctl
= 0x4536393b,
168 .p1_mprddlctl
= 0x36353441,
169 .p0_mpwrdlctl
= 0x41414743,
170 .p1_mpwrdlctl
= 0x462f453f,
174 static struct mx6_ddr_sysinfo mem_q
= {
177 /* config for full 4GB range so that get_mem_size() works */
190 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib
= {
191 .p0_mpwldectrl0
= 0x001f001f,
192 .p0_mpwldectrl1
= 0x001f001f,
193 .p1_mpwldectrl0
= 0x001f001f,
194 .p1_mpwldectrl1
= 0x001f001f,
195 .p0_mpdgctrl0
= 0x420e020e,
196 .p0_mpdgctrl1
= 0x02000200,
197 .p1_mpdgctrl0
= 0x42020202,
198 .p1_mpdgctrl1
= 0x01720172,
199 .p0_mprddlctl
= 0x494c4f4c,
200 .p1_mprddlctl
= 0x4a4c4c49,
201 .p0_mpwrdlctl
= 0x3f3f3133,
202 .p1_mpwrdlctl
= 0x39373f2e,
205 static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib
= {
206 .p0_mpwldectrl0
= 0x0040003c,
207 .p0_mpwldectrl1
= 0x0032003e,
208 .p0_mpdgctrl0
= 0x42350231,
209 .p0_mpdgctrl1
= 0x021a0218,
210 .p0_mprddlctl
= 0x4b4b4e49,
211 .p0_mpwrdlctl
= 0x3f3f3035,
215 static struct mx6_ddr_sysinfo mem_dl
= {
218 /* config for full 4GB range so that get_mem_size() works */
231 /* DDR 32bit 512MB */
232 static struct mx6_ddr_sysinfo mem_s
= {
235 /* config for full 4GB range so that get_mem_size() works */
248 static void ccgr_init(void)
250 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
252 writel(0x00C03F3F, &ccm
->CCGR0
);
253 writel(0x0030FC03, &ccm
->CCGR1
);
254 writel(0x0FFFC000, &ccm
->CCGR2
);
255 writel(0x3FF00000, &ccm
->CCGR3
);
256 writel(0x00FFF300, &ccm
->CCGR4
);
257 writel(0x0F0000C3, &ccm
->CCGR5
);
258 writel(0x000003FF, &ccm
->CCGR6
);
261 static void spl_dram_init(void)
263 if (is_cpu_type(MXC_CPU_MX6SOLO
)) {
264 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
265 mx6_dram_cfg(&mem_s
, &mx6s_512m_mmdc_calib
, &h5tq2g63dfr
);
266 } else if (is_cpu_type(MXC_CPU_MX6DL
)) {
267 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
268 mx6_dram_cfg(&mem_dl
, &mx6dl_1g_mmdc_calib
, &h5tq2g63dfr
);
269 } else if (is_cpu_type(MXC_CPU_MX6Q
)) {
270 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs
, &mx6dq_grp_ioregs
);
271 mx6_dram_cfg(&mem_q
, &mx6q_2g_mmdc_calib
, &h5t04g63afr
);
277 void board_init_f(ulong dummy
)
281 /* setup AIPS and disable watchdog */
287 board_early_init_f();
292 /* UART clocks enabled and gd valid - init serial console */
293 preloader_console_init();
295 /* DDR initialization */