board/lpc2292sodimm/eth.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License as
   4  * published by the Free Software Foundation; either version 2 of
   5  * the License, or (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  15  * MA 02111-1307 USA
  16  */
  17
  18 #include <config.h>
  19 #include <common.h>
  20 #include <net.h>
  21 #include <asm/arch/hardware.h>
  22 #include "spi.h"
  23
  24 /*
  25  * Control Registers in Bank 0
  26  */
  27
  28 #define CTL_REG_ERDPTL   0x00
  29 #define CTL_REG_ERDPTH   0x01
  30 #define CTL_REG_EWRPTL   0x02
  31 #define CTL_REG_EWRPTH   0x03
  32 #define CTL_REG_ETXSTL   0x04
  33 #define CTL_REG_ETXSTH   0x05
  34 #define CTL_REG_ETXNDL   0x06
  35 #define CTL_REG_ETXNDH   0x07
  36 #define CTL_REG_ERXSTL   0x08
  37 #define CTL_REG_ERXSTH   0x09
  38 #define CTL_REG_ERXNDL   0x0A
  39 #define CTL_REG_ERXNDA   0x0B
  40 #define CTL_REG_ERXRDPTL 0x0C
  41 #define CTL_REG_ERXRDPTH 0x0D
  42 #define CTL_REG_ERXWRPTL 0x0E
  43 #define CTL_REG_ERXWRPTH 0x0F
  44 #define CTL_REG_EDMASTL  0x10
  45 #define CTL_REG_EDMASTH  0x11
  46 #define CTL_REG_EDMANDL  0x12
  47 #define CTL_REG_EDMANDH  0x13
  48 #define CTL_REG_EDMADSTL 0x14
  49 #define CTL_REG_EDMADSTH 0x15
  50 #define CTL_REG_EDMACSL  0x16
  51 #define CTL_REG_EDMACSH  0x17
  52 /* these are common in all banks */
  53 #define CTL_REG_EIE      0x1B
  54 #define CTL_REG_EIR      0x1C
  55 #define CTL_REG_ESTAT    0x1D
  56 #define CTL_REG_ECON2    0x1E
  57 #define CTL_REG_ECON1    0x1F
  58
  59 /*
  60  * Control Registers in Bank 1
  61  */
  62
  63 #define CTL_REG_EHT0    0x00
  64 #define CTL_REG_EHT1    0x01
  65 #define CTL_REG_EHT2    0x02
  66 #define CTL_REG_EHT3    0x03
  67 #define CTL_REG_EHT4    0x04
  68 #define CTL_REG_EHT5    0x05
  69 #define CTL_REG_EHT6    0x06
  70 #define CTL_REG_EHT7    0x07
  71 #define CTL_REG_EPMM0   0x08
  72 #define CTL_REG_EPMM1   0x09
  73 #define CTL_REG_EPMM2   0x0A
  74 #define CTL_REG_EPMM3   0x0B
  75 #define CTL_REG_EPMM4   0x0C
  76 #define CTL_REG_EPMM5   0x0D
  77 #define CTL_REG_EPMM6   0x0E
  78 #define CTL_REG_EPMM7   0x0F
  79 #define CTL_REG_EPMCSL  0x10
  80 #define CTL_REG_EPMCSH  0x11
  81 #define CTL_REG_EPMOL   0x14
  82 #define CTL_REG_EPMOH   0x15
  83 #define CTL_REG_EWOLIE  0x16
  84 #define CTL_REG_EWOLIR  0x17
  85 #define CTL_REG_ERXFCON 0x18
  86 #define CTL_REG_EPKTCNT 0x19
  87
  88 /*
  89  * Control Registers in Bank 2
  90  */
  91
  92 #define CTL_REG_MACON1   0x00
  93 #define CTL_REG_MACON2   0x01
  94 #define CTL_REG_MACON3   0x02
  95 #define CTL_REG_MACON4   0x03
  96 #define CTL_REG_MABBIPG  0x04
  97 #define CTL_REG_MAIPGL   0x06
  98 #define CTL_REG_MAIPGH   0x07
  99 #define CTL_REG_MACLCON1 0x08
 100 #define CTL_REG_MACLCON2 0x09
 101 #define CTL_REG_MAMXFLL  0x0A
 102 #define CTL_REG_MAMXFLH  0x0B
 103 #define CTL_REG_MAPHSUP  0x0D
 104 #define CTL_REG_MICON    0x11
 105 #define CTL_REG_MICMD    0x12
 106 #define CTL_REG_MIREGADR 0x14
 107 #define CTL_REG_MIWRL    0x16
 108 #define CTL_REG_MIWRH    0x17
 109 #define CTL_REG_MIRDL    0x18
 110 #define CTL_REG_MIRDH    0x19
 111
 112 /*
 113  * Control Registers in Bank 3
 114  */
 115
 116 #define CTL_REG_MAADR1  0x00
 117 #define CTL_REG_MAADR0  0x01
 118 #define CTL_REG_MAADR3  0x02
 119 #define CTL_REG_MAADR2  0x03
 120 #define CTL_REG_MAADR5  0x04
 121 #define CTL_REG_MAADR4  0x05
 122 #define CTL_REG_EBSTSD  0x06
 123 #define CTL_REG_EBSTCON 0x07
 124 #define CTL_REG_EBSTCSL 0x08
 125 #define CTL_REG_EBSTCSH 0x09
 126 #define CTL_REG_MISTAT  0x0A
 127 #define CTL_REG_EREVID  0x12
 128 #define CTL_REG_ECOCON  0x15
 129 #define CTL_REG_EFLOCON 0x17
 130 #define CTL_REG_EPAUSL  0x18
 131 #define CTL_REG_EPAUSH  0x19
 132
 133
 134 /*
 135  * PHY Register
 136  */
 137
 138 #define PHY_REG_PHID1 0x02
 139 #define PHY_REG_PHID2 0x03
 140
 141
 142 /*
 143  * Receive Filter Register (ERXFCON) bits
 144  */
 145
 146 #define ENC_RFR_UCEN  0x80
 147 #define ENC_RFR_ANDOR 0x40
 148 #define ENC_RFR_CRCEN 0x20
 149 #define ENC_RFR_PMEN  0x10
 150 #define ENC_RFR_MPEN  0x08
 151 #define ENC_RFR_HTEN  0x04
 152 #define ENC_RFR_MCEN  0x02
 153 #define ENC_RFR_BCEN  0x01
 154
 155 /*
 156  * ECON1 Register Bits
 157  */
 158
 159 #define ENC_ECON1_TXRST  0x80
 160 #define ENC_ECON1_RXRST  0x40
 161 #define ENC_ECON1_DMAST  0x20
 162 #define ENC_ECON1_CSUMEN 0x10
 163 #define ENC_ECON1_TXRTS  0x08
 164 #define ENC_ECON1_RXEN   0x04
 165 #define ENC_ECON1_BSEL1  0x02
 166 #define ENC_ECON1_BSEL0  0x01
 167
 168 /*
 169  * ECON2 Register Bits
 170  */
 171 #define ENC_ECON2_AUTOINC 0x80
 172 #define ENC_ECON2_PKTDEC  0x40
 173 #define ENC_ECON2_PWRSV   0x20
 174 #define ENC_ECON2_VRPS    0x08
 175
 176 /*
 177  * EIR Register Bits
 178  */
 179 #define ENC_EIR_PKTIF  0x40
 180 #define ENC_EIR_DMAIF  0x20
 181 #define ENC_EIR_LINKIF 0x10
 182 #define ENC_EIR_TXIF   0x08
 183 #define ENC_EIR_WOLIF  0x04
 184 #define ENC_EIR_TXERIF 0x02
 185 #define ENC_EIR_RXERIF 0x01
 186
 187 /*
 188  * ESTAT Register Bits
 189  */
 190
 191 #define ENC_ESTAT_INT     0x80
 192 #define ENC_ESTAT_LATECOL 0x10
 193 #define ENC_ESTAT_RXBUSY  0x04
 194 #define ENC_ESTAT_TXABRT  0x02
 195 #define ENC_ESTAT_CLKRDY  0x01
 196
 197 /*
 198  * EIE Register Bits
 199  */
 200
 201 #define ENC_EIE_INTIE  0x80
 202 #define ENC_EIE_PKTIE  0x40
 203 #define ENC_EIE_DMAIE  0x20
 204 #define ENC_EIE_LINKIE 0x10
 205 #define ENC_EIE_TXIE   0x08
 206 #define ENC_EIE_WOLIE  0x04
 207 #define ENC_EIE_TXERIE 0x02
 208 #define ENC_EIE_RXERIE 0x01
 209
 210 /*
 211  * MACON1 Register Bits
 212  */
 213 #define ENC_MACON1_LOOPBK  0x10
 214 #define ENC_MACON1_TXPAUS  0x08
 215 #define ENC_MACON1_RXPAUS  0x04
 216 #define ENC_MACON1_PASSALL 0x02
 217 #define ENC_MACON1_MARXEN  0x01
 218
 219
 220 /*
 221  * MACON2 Register Bits
 222  */
 223 #define ENC_MACON2_MARST   0x80
 224 #define ENC_MACON2_RNDRST  0x40
 225 #define ENC_MACON2_MARXRST 0x08
 226 #define ENC_MACON2_RFUNRST 0x04
 227 #define ENC_MACON2_MATXRST 0x02
 228 #define ENC_MACON2_TFUNRST 0x01
 229
 230 /*
 231  * MACON3 Register Bits
 232  */
 233 #define ENC_MACON3_PADCFG2 0x80
 234 #define ENC_MACON3_PADCFG1 0x40
 235 #define ENC_MACON3_PADCFG0 0x20
 236 #define ENC_MACON3_TXCRCEN 0x10
 237 #define ENC_MACON3_PHDRLEN 0x08
 238 #define ENC_MACON3_HFRMEN  0x04
 239 #define ENC_MACON3_FRMLNEN 0x02
 240 #define ENC_MACON3_FULDPX  0x01
 241
 242 /*
 243  * MICMD Register Bits
 244  */
 245 #define ENC_MICMD_MIISCAN 0x02
 246 #define ENC_MICMD_MIIRD   0x01
 247
 248 /*
 249  * MISTAT Register Bits
 250  */
 251 #define ENC_MISTAT_NVALID 0x04
 252 #define ENC_MISTAT_SCAN   0x02
 253 #define ENC_MISTAT_BUSY   0x01
 254
 255 /*
 256  * PHID1 and PHID2 values
 257  */
 258 #define ENC_PHID1_VALUE 0x0083
 259 #define ENC_PHID2_VALUE 0x1400
 260 #define ENC_PHID2_MASK  0xFC00
 261
 262
 263 #define ENC_SPI_SLAVE_CS 0x00010000     /* pin P1.16 */
 264 #define ENC_RESET        0x00020000     /* pin P1.17 */
 265
 266 #define FAILSAFE_VALUE 5000
 267
 268 /*
 269  * Controller memory layout:
 270  *
 271  * 0x0000 - 0x17ff  6k bytes receive buffer
 272  * 0x1800 - 0x1fff  2k bytes transmit buffer
 273  */
 274 /* Use the lower memory for receiver buffer. See errata pt. 5 */
 275 #define ENC_RX_BUF_START 0x0000
 276 #define ENC_TX_BUF_START 0x1800
 277
 278 /* maximum frame length */
 279 #define ENC_MAX_FRM_LEN 1518
 280
 281 #define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
 282 #define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
 283 #define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
 284
 285
 286 static unsigned char encReadReg (unsigned char regNo);
 287 static void encWriteReg (unsigned char regNo, unsigned char data);
 288 static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c);
 289 static void encReadBuff (unsigned short length, unsigned char *pBuff);
 290 static void encWriteBuff (unsigned short length, unsigned char *pBuff);
 291 static void encBitSet (unsigned char regNo, unsigned char data);
 292 static void encBitClr (unsigned char regNo, unsigned char data);
 293 static void encReset (void);
 294 static void encInit (unsigned char *pEthAddr);
 295 static unsigned short phyRead (unsigned char addr);
 296 static void encPoll (void);
 297 static void encRx (void);
 298
 299 #define m_nic_read(reg) encReadReg(reg)
 300 #define m_nic_write(reg, data) encWriteReg(reg, data)
 301 #define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count)
 302 #define m_nic_read_data(len, buf) encReadBuff((len), (buf))
 303 #define m_nic_write_data(len, buf) encWriteBuff((len), (buf))
 304
 305 /* bit field set */
 306 #define m_nic_bfs(reg, data) encBitSet(reg, data)
 307
 308 /* bit field clear */
 309 #define m_nic_bfc(reg, data) encBitClr(reg, data)
 310
 311 static unsigned char bank = 0;  /* current bank in enc28j60 */
 312 static unsigned char next_pointer_lsb;
 313 static unsigned char next_pointer_msb;
 314
 315 static unsigned char buffer[ENC_MAX_FRM_LEN];
 316 static int rxResetCounter = 0;
 317
 318 #define RX_RESET_COUNTER 1000;
 319
 320 /*-----------------------------------------------------------------------------
 321  * Returns 0 when failes otherwize 1
 322  */
 323 int eth_init (bd_t * bis)
 324 {
 325         /* configure GPIO */
 326         (*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
 327         (*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
 328
 329         /* CS and RESET active low */
 330         PUT32 (IO1SET, ENC_SPI_SLAVE_CS);
 331         PUT32 (IO1SET, ENC_RESET);
 332
 333         spi_init ();
 334
 335         /* initialize controller */
 336         encReset ();
 337         encInit (bis->bi_enetaddr);
 338
 339         m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN);      /* enable receive */
 340
 341         return 0;
 342 }
 343
 344 int eth_send (volatile void *packet, int length)
 345 {
 346         /* check frame length, etc. */
 347         /* TODO: */
 348
 349         /* switch to bank 0 */
 350         m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
 351
 352         /* set EWRPT */
 353         m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
 354         m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
 355
 356         /* set ETXST */
 357         m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
 358         m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
 359
 360         /* write packet */
 361         m_nic_write_data (length, (unsigned char *) packet);
 362
 363         /* set ETXND */
 364         m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
 365         m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
 366
 367         /* set ECON1.TXRTS */
 368         m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
 369
 370         return 0;
 371 }
 372
 373
 374 /*****************************************************************************
 375  * This function resets the receiver only. This function may be called from
 376  * interrupt-context.
 377  */
 378 static void encReceiverReset (void)
 379 {
 380         unsigned char econ1;
 381
 382         econ1 = m_nic_read (CTL_REG_ECON1);
 383         if ((econ1 & ENC_ECON1_RXRST) == 0) {
 384                 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST);
 385                 rxResetCounter = RX_RESET_COUNTER;
 386         }
 387 }
 388
 389 /*****************************************************************************
 390  * receiver reset timer
 391  */
 392 static void encReceiverResetCallback (void)
 393 {
 394         m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST);
 395         m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN);      /* enable receive */
 396 }
 397
 398 /*-----------------------------------------------------------------------------
 399  * Check for received packets. Call NetReceive for each packet. The return
 400  * value is ignored by the caller.
 401  */
 402 int eth_rx (void)
 403 {
 404         if (rxResetCounter > 0 && --rxResetCounter == 0) {
 405                 encReceiverResetCallback ();
 406         }
 407
 408         encPoll ();
 409
 410         return 0;
 411 }
 412
 413 void eth_halt (void)
 414 {
 415         m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN);      /* disable receive */
 416 }
 417
 418 /*****************************************************************************/
 419
 420 static void encPoll (void)
 421 {
 422         unsigned char eir_reg;
 423         volatile unsigned char estat_reg;
 424         unsigned char pkt_cnt;
 425
 426         /* clear global interrupt enable bit in enc28j60 */
 427         m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
 428         estat_reg = m_nic_read (CTL_REG_ESTAT);
 429
 430         eir_reg = m_nic_read (CTL_REG_EIR);
 431
 432         if (eir_reg & ENC_EIR_TXIF) {
 433                 /* clear TXIF bit in EIR */
 434                 m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF);
 435         }
 436
 437         /* We have to use pktcnt and not pktif bit, see errata pt. 6 */
 438
 439         /* move to bank 1 */
 440         m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
 441         m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
 442
 443         /* read pktcnt */
 444         pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
 445
 446         if (pkt_cnt > 0) {
 447                 if ((eir_reg & ENC_EIR_PKTIF) == 0) {
 448                         /*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */
 449                 }
 450                 encRx ();
 451                 /* clear PKTIF bit in EIR, this should not need to be done but it
 452                    seems like we get problems if we do not */
 453                 m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF);
 454         }
 455
 456         if (eir_reg & ENC_EIR_RXERIF) {
 457                 printf ("encPoll: rx error\n");
 458                 m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF);
 459         }
 460         if (eir_reg & ENC_EIR_TXERIF) {
 461                 printf ("encPoll: tx error\n");
 462                 m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
 463         }
 464
 465         /* set global interrupt enable bit in enc28j60 */
 466         m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
 467 }
 468
 469 static void encRx (void)
 470 {
 471         unsigned short pkt_len;
 472         unsigned short copy_len;
 473         unsigned short status;
 474         unsigned char eir_reg;
 475         unsigned char pkt_cnt = 0;
 476
 477         /* switch to bank 0 */
 478         m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
 479
 480         m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
 481         m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
 482
 483         do {
 484                 m_nic_read_data (6, buffer);
 485                 next_pointer_lsb = buffer[0];
 486                 next_pointer_msb = buffer[1];
 487                 pkt_len = buffer[2];
 488                 pkt_len |= (unsigned short) buffer[3] << 8;
 489                 status = buffer[4];
 490                 status |= (unsigned short) buffer[5] << 8;
 491
 492                 if (pkt_len <= ENC_MAX_FRM_LEN) {
 493                         copy_len = pkt_len;
 494                 } else {
 495                         copy_len = 0;
 496                         /*      p_priv->stats.rx_dropped++; */
 497                         /* we will drop this packet */
 498                 }
 499
 500                 if ((status & (1L << 7)) == 0) {        /* check Received Ok bit */
 501                         copy_len = 0;
 502                         /*      p_priv->stats.rx_errors++; */
 503                 }
 504
 505                 if (copy_len > 0) {
 506                         m_nic_read_data (copy_len, buffer);
 507                 }
 508
 509                 /* advance read pointer to next pointer */
 510                 m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
 511                 m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
 512
 513                 /* decrease packet counter */
 514                 m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
 515
 516                 /* move to bank 1 */
 517                 m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
 518                 m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
 519
 520                 /* read pktcnt */
 521                 pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
 522
 523                 /* switch to bank 0 */
 524                 m_nic_bfc (CTL_REG_ECON1,
 525                            (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
 526
 527                 if (copy_len == 0) {
 528                         eir_reg = m_nic_read (CTL_REG_EIR);
 529                         encReceiverReset ();
 530                         printf ("eth_rx: copy_len=0\n");
 531                         continue;
 532                 }
 533
 534                 NetReceive ((unsigned char *) buffer, pkt_len);
 535
 536                 eir_reg = m_nic_read (CTL_REG_EIR);
 537         } while (pkt_cnt);      /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
 538         m_nic_write (CTL_REG_ERXRDPTL, next_pointer_lsb);
 539         m_nic_write (CTL_REG_ERXRDPTH, next_pointer_msb);
 540 }
 541
 542 static void encWriteReg (unsigned char regNo, unsigned char data)
 543 {
 544         spi_lock ();
 545         enc_cfg_spi ();
 546         enc_enable ();
 547
 548         spi_write (0x40 | regNo);       /* write in regNo */
 549         spi_write (data);
 550
 551         enc_disable ();
 552         enc_enable ();
 553
 554         spi_write (0x1f);       /* write reg 0x1f */
 555
 556         enc_disable ();
 557         spi_unlock ();
 558 }
 559
 560 static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c)
 561 {
 562         unsigned char readback;
 563         int i;
 564
 565         spi_lock ();
 566
 567         for (i = 0; i < c; i++) {
 568                 enc_cfg_spi ();
 569                 enc_enable ();
 570
 571                 spi_write (0x40 | regNo);       /* write in regNo */
 572                 spi_write (data);
 573
 574                 enc_disable ();
 575                 enc_enable ();
 576
 577                 spi_write (0x1f);       /* write reg 0x1f */
 578
 579                 enc_disable ();
 580
 581                 spi_unlock ();  /* we must unlock spi first */
 582
 583                 readback = encReadReg (regNo);
 584
 585                 spi_lock ();
 586
 587                 if (readback == data)
 588                         break;
 589         }
 590         spi_unlock ();
 591
 592         if (i == c) {
 593                 printf ("enc28j60: write reg %d failed\n", regNo);
 594         }
 595 }
 596
 597 static unsigned char encReadReg (unsigned char regNo)
 598 {
 599         unsigned char rxByte;
 600
 601         spi_lock ();
 602         enc_cfg_spi ();
 603         enc_enable ();
 604
 605         spi_write (0x1f);       /* read reg 0x1f */
 606
 607         bank = spi_read () & 0x3;
 608
 609         enc_disable ();
 610         enc_enable ();
 611
 612         spi_write (regNo);
 613         rxByte = spi_read ();
 614
 615         /* check if MAC or MII register */
 616         if (((bank == 2) && (regNo <= 0x1a)) ||
 617             ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) {
 618                 /* ignore first byte and read another byte */
 619                 rxByte = spi_read ();
 620         }
 621
 622         enc_disable ();
 623         spi_unlock ();
 624
 625         return rxByte;
 626 }
 627
 628 static void encReadBuff (unsigned short length, unsigned char *pBuff)
 629 {
 630         spi_lock ();
 631         enc_cfg_spi ();
 632         enc_enable ();
 633
 634         spi_write (0x20 | 0x1a);        /* read buffer memory */
 635
 636         while (length--) {
 637                 if (pBuff != NULL)
 638                         *pBuff++ = spi_read ();
 639                 else
 640                         spi_write (0);
 641         }
 642
 643         enc_disable ();
 644         spi_unlock ();
 645 }
 646
 647 static void encWriteBuff (unsigned short length, unsigned char *pBuff)
 648 {
 649         spi_lock ();
 650         enc_cfg_spi ();
 651         enc_enable ();
 652
 653         spi_write (0x60 | 0x1a);        /* write buffer memory */
 654
 655         spi_write (0x00);       /* control byte */
 656
 657         while (length--)
 658                 spi_write (*pBuff++);
 659
 660         enc_disable ();
 661         spi_unlock ();
 662 }
 663
 664 static void encBitSet (unsigned char regNo, unsigned char data)
 665 {
 666         spi_lock ();
 667         enc_cfg_spi ();
 668         enc_enable ();
 669
 670         spi_write (0x80 | regNo);       /* bit field set */
 671         spi_write (data);
 672
 673         enc_disable ();
 674         spi_unlock ();
 675 }
 676
 677 static void encBitClr (unsigned char regNo, unsigned char data)
 678 {
 679         spi_lock ();
 680         enc_cfg_spi ();
 681         enc_enable ();
 682
 683         spi_write (0xA0 | regNo);       /* bit field clear */
 684         spi_write (data);
 685
 686         enc_disable ();
 687         spi_unlock ();
 688 }
 689
 690 static void encReset (void)
 691 {
 692         spi_lock ();
 693         enc_cfg_spi ();
 694         enc_enable ();
 695
 696         spi_write (0xff);       /* soft reset */
 697
 698         enc_disable ();
 699         spi_unlock ();
 700
 701         /* sleep 1 ms. See errata pt. 2 */
 702         udelay (1000);
 703
 704 #if 0
 705         (*((volatile unsigned long *) IO1CLR)) &= ENC_RESET;
 706         mdelay (5);
 707         (*((volatile unsigned long *) IO1SET)) &= ENC_RESET;
 708 #endif
 709 }
 710
 711 static void encInit (unsigned char *pEthAddr)
 712 {
 713         unsigned short phid1 = 0;
 714         unsigned short phid2 = 0;
 715
 716         /* switch to bank 0 */
 717         m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
 718
 719         /*
 720          * Setup the buffer space. The reset values are valid for the
 721          * other pointers.
 722          */
 723 #if 0
 724         /* We shall not write to ERXST, see errata pt. 5. Instead we
 725            have to make sure that ENC_RX_BUS_START is 0. */
 726         m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
 727         m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
 728 #endif
 729         m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
 730         m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
 731
 732         next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
 733         next_pointer_msb = (ENC_RX_BUF_START >> 8);
 734
 735         /*
 736          * For tracking purposes, the ERXRDPT registers should be programmed with
 737          * the same value. This is the read pointer.
 738          */
 739         m_nic_write (CTL_REG_ERXRDPTL, (ENC_RX_BUF_START & 0xFF));
 740         m_nic_write_retry (CTL_REG_ERXRDPTH, (ENC_RX_BUF_START >> 8), 1);
 741
 742         /* Setup receive filters. */
 743
 744         /* move to bank 1 */
 745         m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
 746         m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
 747
 748         /* OR-filtering, Unicast, CRC-check and broadcast */
 749         m_nic_write_retry (CTL_REG_ERXFCON,
 750                            (ENC_RFR_UCEN | ENC_RFR_CRCEN | ENC_RFR_BCEN), 1);
 751
 752         /* Wait for Oscillator Start-up Timer (OST). */
 753         while ((m_nic_read (CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) == 0) {
 754                 static int cnt = 0;
 755
 756                 if (cnt++ >= 1000) {
 757                         cnt = 0;
 758                 }
 759         }
 760
 761         /* verify identification */
 762         phid1 = phyRead (PHY_REG_PHID1);
 763         phid2 = phyRead (PHY_REG_PHID2);
 764
 765         if (phid1 != ENC_PHID1_VALUE
 766             || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) {
 767                 printf ("ERROR: failed to identify controller\n");
 768                 printf ("phid1 = %x, phid2 = %x\n",
 769                         phid1, (phid2 & ENC_PHID2_MASK));
 770                 printf ("should be phid1 = %x, phid2 = %x\n",
 771                         ENC_PHID1_VALUE, ENC_PHID2_VALUE);
 772         }
 773
 774         /*
 775          * --- MAC Initialization ---
 776          */
 777
 778         /* Pull MAC out of Reset */
 779
 780         /* switch to bank 2 */
 781         m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
 782         m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
 783         /* clear MAC reset bits */
 784         m_nic_write_retry (CTL_REG_MACON2, 0, 1);
 785
 786         /* enable MAC to receive frames */
 787         m_nic_write_retry (CTL_REG_MACON1, ENC_MACON1_MARXEN, 10);
 788
 789         /* configure pad, tx-crc and duplex */
 790         /* TODO maybe enable FRMLNEN */
 791         m_nic_write_retry (CTL_REG_MACON3,
 792                            (ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN), 10);
 793
 794         /* set maximum frame length */
 795         m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
 796         m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10);
 797
 798         /*
 799          * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex
 800          * and 0x15 for full duplex.
 801          */
 802         m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
 803
 804         /* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
 805         m_nic_write_retry (CTL_REG_MAIPGL, 0x12, 10);
 806
 807         /*
 808          * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
 809          * 0x0c for half-duplex. Nothing for full-duplex
 810          */
 811         m_nic_write_retry (CTL_REG_MAIPGH, 0x0C, 10);
 812
 813         /* set MAC address */
 814
 815         /* switch to bank 3 */
 816         m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1));
 817
 818         m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1);
 819         m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1);
 820         m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1);
 821         m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1);
 822         m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1);
 823         m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
 824
 825         /*
 826          * Receive settings
 827          */
 828
 829         /* auto-increment RX-pointer when reading a received packet */
 830         m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_AUTOINC);
 831
 832         /* enable interrupts */
 833         m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
 834         m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
 835         m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
 836         m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
 837         m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
 838 }
 839
 840 /*****************************************************************************
 841  *
 842  * Description:
 843  *    Read PHY registers.
 844  *
 845  *    NOTE! This function will change to Bank 2.
 846  *
 847  * Params:
 848  *    [in] addr address of the register to read
 849  *
 850  * Returns:
 851  *    The value in the register
 852  */
 853 static unsigned short phyRead (unsigned char addr)
 854 {
 855         unsigned short ret = 0;
 856
 857         /* move to bank 2 */
 858         m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
 859         m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
 860
 861         /* write address to MIREGADR */
 862         m_nic_write (CTL_REG_MIREGADR, addr);
 863
 864         /* set MICMD.MIIRD */
 865         m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
 866
 867         /* poll MISTAT.BUSY bit until operation is complete */
 868         while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
 869                 static int cnt = 0;
 870
 871                 if (cnt++ >= 1000) {
 872                         /* GJ - this seems extremely dangerous! */
 873                         /* printf("#"); */
 874                         cnt = 0;
 875                 }
 876         }
 877
 878         /* clear MICMD.MIIRD */
 879         m_nic_write (CTL_REG_MICMD, 0);
 880
 881         ret = (m_nic_read (CTL_REG_MIRDH) << 8);
 882         ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF);
 883
 884         return ret;
 885 }