board/lwmon5/sdram.c

   1 /*
   2  * (C) Copyright 2006
   3  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
   4  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   5  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
   6  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   7  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
   8  *
   9  * (C) Copyright 2007-2013
  10  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 /* define DEBUG for debugging output (obviously ;-)) */
  16 #if 0
  17 #define DEBUG
  18 #endif
  19
  20 #include <common.h>
  21 #include <asm/processor.h>
  22 #include <asm/mmu.h>
  23 #include <asm/io.h>
  24 #include <asm/cache.h>
  25 #include <asm/ppc440.h>
  26 #include <watchdog.h>
  27
  28 /*
  29  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  30  * region. Right now the cache should still be disabled in U-Boot because of the
  31  * EMAC driver, that need it's buffer descriptor to be located in non cached
  32  * memory.
  33  *
  34  * If at some time this restriction doesn't apply anymore, just define
  35  * CONFIG_4xx_DCACHE in the board config file and this code should setup
  36  * everything correctly.
  37  */
  38 #ifdef CONFIG_4xx_DCACHE
  39 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
  40 #else
  41 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
  42 #endif
  43
  44 /*-----------------------------------------------------------------------------+
  45  * Prototypes
  46  *-----------------------------------------------------------------------------*/
  47 extern int denali_wait_for_dlllock(void);
  48 extern void denali_core_search_data_eye(void);
  49 extern void dcbz_area(u32 start_address, u32 num_bytes);
  50
  51 static u32 is_ecc_enabled(void)
  52 {
  53         u32 val;
  54
  55         mfsdram(DDR0_22, val);
  56         val &= DDR0_22_CTRL_RAW_MASK;
  57         if (val)
  58                 return 1;
  59         else
  60                 return 0;
  61 }
  62
  63 void board_add_ram_info(int use_default)
  64 {
  65         PPC4xx_SYS_INFO board_cfg;
  66         u32 val;
  67
  68         if (is_ecc_enabled())
  69                 puts(" (ECC");
  70         else
  71                 puts(" (ECC not");
  72
  73         get_sys_info(&board_cfg);
  74         printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
  75
  76         mfsdram(DDR0_03, val);
  77         val = DDR0_03_CASLAT_DECODE(val);
  78         printf(", CL%d)", val);
  79 }
  80
  81 #ifdef CONFIG_DDR_ECC
  82 static void wait_ddr_idle(void)
  83 {
  84         /*
  85          * Controller idle status cannot be determined for Denali
  86          * DDR2 code. Just return here.
  87          */
  88 }
  89
  90 static void program_ecc(u32 start_address,
  91                         u32 num_bytes,
  92                         u32 tlb_word2_i_value)
  93 {
  94         u32 val;
  95         u32 current_addr = start_address;
  96         u32 size;
  97         int bytes_remaining;
  98
  99         sync();
 100         wait_ddr_idle();
 101
 102         /*
 103          * Because of 440EPx errata CHIP 11, we don't touch the last 256
 104          * bytes of SDRAM.
 105          */
 106         bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
 107
 108         /*
 109          * We have to write the ECC bytes by zeroing and flushing in smaller
 110          * steps, since the whole 256MByte takes too long for the external
 111          * watchdog.
 112          */
 113         while (bytes_remaining > 0) {
 114                 size = min((64 << 20), bytes_remaining);
 115
 116                 /* Write zero's to SDRAM */
 117                 dcbz_area(current_addr, size);
 118
 119                 /* Write modified dcache lines back to memory */
 120                 clean_dcache_range(current_addr, current_addr + size);
 121
 122                 current_addr += 64 << 20;
 123                 bytes_remaining -= 64 << 20;
 124                 WATCHDOG_RESET();
 125         }
 126
 127         sync();
 128         wait_ddr_idle();
 129
 130         /* Clear error status */
 131         mfsdram(DDR0_00, val);
 132         mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
 133
 134         /* Set 'int_mask' parameter to functionnal value */
 135         mfsdram(DDR0_01, val);
 136         mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
 137
 138         sync();
 139         wait_ddr_idle();
 140 }
 141 #endif
 142
 143 /*************************************************************************
 144  *
 145  * initdram -- 440EPx's DDR controller is a DENALI Core
 146  *
 147  ************************************************************************/
 148 phys_size_t initdram (int board_type)
 149 {
 150         /* CL=4 */
 151         mtsdram(DDR0_02, 0x00000000);
 152
 153         mtsdram(DDR0_00, 0x0000190A);
 154         mtsdram(DDR0_01, 0x01000000);
 155         mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
 156
 157         mtsdram(DDR0_04, 0x0B030300);
 158         mtsdram(DDR0_05, 0x02020308);
 159         mtsdram(DDR0_06, 0x0003C812);
 160         mtsdram(DDR0_07, 0x00090100);
 161         mtsdram(DDR0_08, 0x03c80001);
 162         mtsdram(DDR0_09, 0x00011D5F);
 163         mtsdram(DDR0_10, 0x00000100);
 164         mtsdram(DDR0_11, 0x000CC800);
 165         mtsdram(DDR0_12, 0x00000003);
 166         mtsdram(DDR0_14, 0x00000000);
 167         mtsdram(DDR0_17, 0x1e000000);
 168         mtsdram(DDR0_18, 0x1e1e1e1e);
 169         mtsdram(DDR0_19, 0x1e1e1e1e);
 170         mtsdram(DDR0_20, 0x0B0B0B0B);
 171         mtsdram(DDR0_21, 0x0B0B0B0B);
 172 #ifdef CONFIG_DDR_ECC
 173         mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
 174 #else
 175         mtsdram(DDR0_22, 0x00267F0B);
 176 #endif
 177
 178         mtsdram(DDR0_23, 0x01000000);
 179         mtsdram(DDR0_24, 0x01010001);
 180
 181         mtsdram(DDR0_26, 0x2D93028A);
 182         mtsdram(DDR0_27, 0x0784682B);
 183
 184         mtsdram(DDR0_28, 0x00000080);
 185         mtsdram(DDR0_31, 0x00000000);
 186         mtsdram(DDR0_42, 0x01000008);
 187
 188         mtsdram(DDR0_43, 0x050A0200);
 189         mtsdram(DDR0_44, 0x00000005);
 190         mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
 191
 192         denali_wait_for_dlllock();
 193
 194 #if defined(CONFIG_DDR_DATA_EYE)
 195         /* -----------------------------------------------------------+
 196          * Perform data eye search if requested.
 197          * ----------------------------------------------------------*/
 198         program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
 199                     TLB_WORD2_I_ENABLE);
 200         denali_core_search_data_eye();
 201         remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
 202 #endif
 203
 204         /*
 205          * Program tlb entries for this size (dynamic)
 206          */
 207         program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
 208                     MY_TLB_WORD2_I_ENABLE);
 209
 210 #if defined(CONFIG_DDR_ECC)
 211 #if defined(CONFIG_4xx_DCACHE)
 212         /*
 213          * If ECC is enabled, initialize the parity bits.
 214          */
 215         program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
 216 #else /* CONFIG_4xx_DCACHE */
 217         /*
 218          * Setup 2nd TLB with same physical address but different virtual address
 219          * with cache enabled. This is done for fast ECC generation.
 220          */
 221         program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
 222
 223         /*
 224          * If ECC is enabled, initialize the parity bits.
 225          */
 226         program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
 227
 228         /*
 229          * Now after initialization (auto-calibration and ECC generation)
 230          * remove the TLB entries with caches enabled and program again with
 231          * desired cache functionality
 232          */
 233         remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
 234 #endif /* CONFIG_4xx_DCACHE */
 235 #endif /* CONFIG_DDR_ECC */
 236
 237         /*
 238          * Clear possible errors resulting from data-eye-search.
 239          * If not done, then we could get an interrupt later on when
 240          * exceptions are enabled.
 241          */
 242         set_mcsr(get_mcsr());
 243
 244         return (CONFIG_SYS_MBYTES_SDRAM << 20);
 245 }