board/lwmon5/sdram.h

   1 /*
   2  * (C) Copyright 2006
   3  * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
   4  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   5  * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
   6  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   7  * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef _SPD_SDRAM_DENALI_H_
  26 #define _SPD_SDRAM_DENALI_H_
  27
  28 #define ppcMsync        sync
  29 #define ppcMbar         eieio
  30
  31 /* General definitions */
  32 #define MAX_SPD_BYTE        128         /* highest SPD byte # to read */
  33 #define DENALI_REG_NUMBER   45          /* 45 Regs in PPC440EPx Denali Core */
  34 #define SUPPORTED_DIMMS_NB  7           /* Number of supported DIMM modules types */
  35 #define SDRAM_NONE          0           /* No DIMM detected in Slot */
  36 #define MAXRANKS            2           /* 2 ranks maximum */
  37
  38 /* Supported PLB Frequencies */
  39 #define PLB_FREQ_133MHZ     133333333
  40 #define PLB_FREQ_152MHZ     152000000
  41 #define PLB_FREQ_160MHZ     160000000
  42 #define PLB_FREQ_166MHZ     166666666
  43
  44 /* Denali Core Registers */
  45 #define SDRAM_DCR_BASE 0x10
  46
  47 #define DDR_DCR_BASE 0x10
  48 #define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
  49 #define ddrcfgd  (DDR_DCR_BASE+0x1)   /* DDR configuration data reg    */
  50
  51 /*-----------------------------------------------------------------------------+
  52   | Values for ddrcfga register - indirect addressing of these regs
  53   +-----------------------------------------------------------------------------*/
  54
  55 #define DDR0_00                         0x00
  56 #define DDR0_00_INT_ACK_MASK              0x7F000000 /* Write only */
  57 #define DDR0_00_INT_ACK_ALL               0x7F000000
  58 #define DDR0_00_INT_ACK_ENCODE(n)           ((((unsigned long)(n))&0x7F)<<24)
  59 #define DDR0_00_INT_ACK_DECODE(n)           ((((unsigned long)(n))>>24)&0x7F)
  60 /* Status */
  61 #define DDR0_00_INT_STATUS_MASK           0x00FF0000 /* Read only */
  62 /* Bit0. A single access outside the defined PHYSICAL memory space detected. */
  63 #define DDR0_00_INT_STATUS_BIT0           0x00010000
  64 /* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
  65 #define DDR0_00_INT_STATUS_BIT1           0x00020000
  66 /* Bit2. Single correctable ECC event detected */
  67 #define DDR0_00_INT_STATUS_BIT2           0x00040000
  68 /* Bit3. Multiple correctable ECC events detected. */
  69 #define DDR0_00_INT_STATUS_BIT3           0x00080000
  70 /* Bit4. Single uncorrectable ECC event detected. */
  71 #define DDR0_00_INT_STATUS_BIT4           0x00100000
  72 /* Bit5. Multiple uncorrectable ECC events detected. */
  73 #define DDR0_00_INT_STATUS_BIT5           0x00200000
  74 /* Bit6. DRAM initialization complete. */
  75 #define DDR0_00_INT_STATUS_BIT6           0x00400000
  76 /* Bit7. Logical OR of all lower bits. */
  77 #define DDR0_00_INT_STATUS_BIT7           0x00800000
  78
  79 #define DDR0_00_INT_STATUS_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
  80 #define DDR0_00_INT_STATUS_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
  81 #define DDR0_00_DLL_INCREMENT_MASK        0x00007F00
  82 #define DDR0_00_DLL_INCREMENT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
  83 #define DDR0_00_DLL_INCREMENT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
  84 #define DDR0_00_DLL_START_POINT_MASK      0x0000007F
  85 #define DDR0_00_DLL_START_POINT_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
  86 #define DDR0_00_DLL_START_POINT_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
  87
  88
  89 #define DDR0_01                         0x01
  90 #define DDR0_01_PLB0_DB_CS_LOWER_MASK     0x1F000000
  91 #define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<24)
  92 #define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n)  ((((unsigned long)(n))>>24)&0x1F)
  93 #define DDR0_01_PLB0_DB_CS_UPPER_MASK     0x001F0000
  94 #define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<16)
  95 #define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n)  ((((unsigned long)(n))>>16)&0x1F)
  96 #define DDR0_01_OUT_OF_RANGE_TYPE_MASK    0x00000700 /* Read only */
  97 #define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n)               ((((unsigned long)(n))&0x7)<<8)
  98 #define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n)               ((((unsigned long)(n))>>8)&0x7)
  99 #define DDR0_01_INT_MASK_MASK             0x000000FF
 100 #define DDR0_01_INT_MASK_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
 101 #define DDR0_01_INT_MASK_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
 102 #define DDR0_01_INT_MASK_ALL_ON           0x000000FF
 103 #define DDR0_01_INT_MASK_ALL_OFF          0x00000000
 104
 105 #define DDR0_02                         0x02
 106 #define DDR0_02_MAX_CS_REG_MASK           0x02000000 /* Read only */
 107 #define DDR0_02_MAX_CS_REG_ENCODE(n)        ((((unsigned long)(n))&0x2)<<24)
 108 #define DDR0_02_MAX_CS_REG_DECODE(n)        ((((unsigned long)(n))>>24)&0x2)
 109 #define DDR0_02_MAX_COL_REG_MASK          0x000F0000 /* Read only */
 110 #define DDR0_02_MAX_COL_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<16)
 111 #define DDR0_02_MAX_COL_REG_DECODE(n)       ((((unsigned long)(n))>>16)&0xF)
 112 #define DDR0_02_MAX_ROW_REG_MASK          0x00000F00 /* Read only */
 113 #define DDR0_02_MAX_ROW_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<8)
 114 #define DDR0_02_MAX_ROW_REG_DECODE(n)       ((((unsigned long)(n))>>8)&0xF)
 115 #define DDR0_02_START_MASK                0x00000001
 116 #define DDR0_02_START_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
 117 #define DDR0_02_START_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
 118 #define DDR0_02_START_OFF                 0x00000000
 119 #define DDR0_02_START_ON                  0x00000001
 120
 121 #define DDR0_03                         0x03
 122 #define DDR0_03_BSTLEN_MASK               0x07000000
 123 #define DDR0_03_BSTLEN_ENCODE(n)            ((((unsigned long)(n))&0x7)<<24)
 124 #define DDR0_03_BSTLEN_DECODE(n)            ((((unsigned long)(n))>>24)&0x7)
 125 #define DDR0_03_CASLAT_MASK               0x00070000
 126 #define DDR0_03_CASLAT_ENCODE(n)            ((((unsigned long)(n))&0x7)<<16)
 127 #define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
 128 #define DDR0_03_CASLAT_LIN_MASK           0x00000F00
 129 #define DDR0_03_CASLAT_LIN_ENCODE(n)        ((((unsigned long)(n))&0xF)<<8)
 130 #define DDR0_03_CASLAT_LIN_DECODE(n)        ((((unsigned long)(n))>>8)&0xF)
 131 #define DDR0_03_INITAREF_MASK             0x0000000F
 132 #define DDR0_03_INITAREF_ENCODE(n)          ((((unsigned long)(n))&0xF)<<0)
 133 #define DDR0_03_INITAREF_DECODE(n)          ((((unsigned long)(n))>>0)&0xF)
 134
 135 #define DDR0_04                         0x04
 136 #define DDR0_04_TRC_MASK                  0x1F000000
 137 #define DDR0_04_TRC_ENCODE(n)               ((((unsigned long)(n))&0x1F)<<24)
 138 #define DDR0_04_TRC_DECODE(n)               ((((unsigned long)(n))>>24)&0x1F)
 139 #define DDR0_04_TRRD_MASK                 0x00070000
 140 #define DDR0_04_TRRD_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
 141 #define DDR0_04_TRRD_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
 142 #define DDR0_04_TRTP_MASK                 0x00000700
 143 #define DDR0_04_TRTP_ENCODE(n)              ((((unsigned long)(n))&0x7)<<8)
 144 #define DDR0_04_TRTP_DECODE(n)              ((((unsigned long)(n))>>8)&0x7)
 145
 146 #define DDR0_05                         0x05
 147 #define DDR0_05_TMRD_MASK                 0x1F000000
 148 #define DDR0_05_TMRD_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<24)
 149 #define DDR0_05_TMRD_DECODE(n)              ((((unsigned long)(n))>>24)&0x1F)
 150 #define DDR0_05_TEMRS_MASK                0x00070000
 151 #define DDR0_05_TEMRS_ENCODE(n)             ((((unsigned long)(n))&0x7)<<16)
 152 #define DDR0_05_TEMRS_DECODE(n)             ((((unsigned long)(n))>>16)&0x7)
 153 #define DDR0_05_TRP_MASK                  0x00000F00
 154 #define DDR0_05_TRP_ENCODE(n)               ((((unsigned long)(n))&0xF)<<8)
 155 #define DDR0_05_TRP_DECODE(n)               ((((unsigned long)(n))>>8)&0xF)
 156 #define DDR0_05_TRAS_MIN_MASK             0x000000FF
 157 #define DDR0_05_TRAS_MIN_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
 158 #define DDR0_05_TRAS_MIN_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
 159
 160 #define DDR0_06                         0x06
 161 #define DDR0_06_WRITEINTERP_MASK          0x01000000
 162 #define DDR0_06_WRITEINTERP_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
 163 #define DDR0_06_WRITEINTERP_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
 164 #define DDR0_06_TWTR_MASK                 0x00070000
 165 #define DDR0_06_TWTR_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
 166 #define DDR0_06_TWTR_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
 167 #define DDR0_06_TDLL_MASK                 0x0000FF00
 168 #define DDR0_06_TDLL_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
 169 #define DDR0_06_TDLL_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
 170 #define DDR0_06_TRFC_MASK                 0x0000007F
 171 #define DDR0_06_TRFC_ENCODE(n)              ((((unsigned long)(n))&0x7F)<<0)
 172 #define DDR0_06_TRFC_DECODE(n)              ((((unsigned long)(n))>>0)&0x7F)
 173
 174 #define DDR0_07                         0x07
 175 #define DDR0_07_NO_CMD_INIT_MASK          0x01000000
 176 #define DDR0_07_NO_CMD_INIT_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
 177 #define DDR0_07_NO_CMD_INIT_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
 178 #define DDR0_07_TFAW_MASK                 0x001F0000
 179 #define DDR0_07_TFAW_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<16)
 180 #define DDR0_07_TFAW_DECODE(n)              ((((unsigned long)(n))>>16)&0x1F)
 181 #define DDR0_07_AUTO_REFRESH_MODE_MASK    0x00000100
 182 #define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
 183 #define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
 184 #define DDR0_07_AREFRESH_MASK             0x00000001
 185 #define DDR0_07_AREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<0)
 186 #define DDR0_07_AREFRESH_DECODE(n)          ((((unsigned long)(n))>>0)&0x1)
 187
 188 #define DDR0_08                         0x08
 189 #define DDR0_08_WRLAT_MASK                0x07000000
 190 #define DDR0_08_WRLAT_ENCODE(n)             ((((unsigned long)(n))&0x7)<<24)
 191 #define DDR0_08_WRLAT_DECODE(n)             ((((unsigned long)(n))>>24)&0x7)
 192 #define DDR0_08_TCPD_MASK                 0x00FF0000
 193 #define DDR0_08_TCPD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<16)
 194 #define DDR0_08_TCPD_DECODE(n)              ((((unsigned long)(n))>>16)&0xFF)
 195 #define DDR0_08_DQS_N_EN_MASK             0x00000100
 196 #define DDR0_08_DQS_N_EN_ENCODE(n)          ((((unsigned long)(n))&0x1)<<8)
 197 #define DDR0_08_DQS_N_EN_DECODE(n)          ((((unsigned long)(n))>>8)&0x1)
 198 #define DDR0_08_DDRII_SDRAM_MODE_MASK     0x00000001
 199 #define DDR0_08_DDRII_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
 200 #define DDR0_08_DDRII_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
 201
 202 #define DDR0_09                         0x09
 203 #define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK  0x1F000000
 204 #define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
 205 #define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
 206 #define DDR0_09_RTT_0_MASK                0x00030000
 207 #define DDR0_09_RTT_0_ENCODE(n)             ((((unsigned long)(n))&0x3)<<16)
 208 #define DDR0_09_RTT_0_DECODE(n)             ((((unsigned long)(n))>>16)&0x3)
 209 #define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK  0x00007F00
 210 #define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
 211 #define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
 212 #define DDR0_09_WR_DQS_SHIFT_MASK         0x0000007F
 213 #define DDR0_09_WR_DQS_SHIFT_ENCODE(n)      ((((unsigned long)(n))&0x7F)<<0)
 214 #define DDR0_09_WR_DQS_SHIFT_DECODE(n)      ((((unsigned long)(n))>>0)&0x7F)
 215
 216 #define DDR0_10                         0x0A
 217 #define DDR0_10_WRITE_MODEREG_MASK        0x00010000 /* Write only */
 218 #define DDR0_10_WRITE_MODEREG_ENCODE(n)     ((((unsigned long)(n))&0x1)<<16)
 219 #define DDR0_10_WRITE_MODEREG_DECODE(n)     ((((unsigned long)(n))>>16)&0x1)
 220 #define DDR0_10_CS_MAP_MASK               0x00000300
 221 #define DDR0_10_CS_MAP_NO_MEM             0x00000000
 222 #define DDR0_10_CS_MAP_RANK0_INSTALLED    0x00000100
 223 #define DDR0_10_CS_MAP_RANK1_INSTALLED    0x00000200
 224 #define DDR0_10_CS_MAP_ENCODE(n)            ((((unsigned long)(n))&0x3)<<8)
 225 #define DDR0_10_CS_MAP_DECODE(n)            ((((unsigned long)(n))>>8)&0x3)
 226 #define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK  0x0000001F
 227 #define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
 228 #define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
 229
 230 #define DDR0_11                         0x0B
 231 #define DDR0_11_SREFRESH_MASK             0x01000000
 232 #define DDR0_11_SREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<24)
 233 #define DDR0_11_SREFRESH_DECODE(n)          ((((unsigned long)(n))>>24)&0x1F)
 234 #define DDR0_11_TXSNR_MASK                0x00FF0000
 235 #define DDR0_11_TXSNR_ENCODE(n)             ((((unsigned long)(n))&0xFF)<<16)
 236 #define DDR0_11_TXSNR_DECODE(n)             ((((unsigned long)(n))>>16)&0xFF)
 237 #define DDR0_11_TXSR_MASK                 0x0000FF00
 238 #define DDR0_11_TXSR_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
 239 #define DDR0_11_TXSR_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
 240
 241 #define DDR0_12                         0x0C
 242 #define DDR0_12_TCKE_MASK                 0x0000007
 243 #define DDR0_12_TCKE_ENCODE(n)              ((((unsigned long)(n))&0x7)<<0)
 244 #define DDR0_12_TCKE_DECODE(n)              ((((unsigned long)(n))>>0)&0x7)
 245
 246 #define DDR0_13                         0x0D
 247
 248 #define DDR0_14                         0x0E
 249 #define DDR0_14_DLL_BYPASS_MODE_MASK      0x01000000
 250 #define DDR0_14_DLL_BYPASS_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<24)
 251 #define DDR0_14_DLL_BYPASS_MODE_DECODE(n)   ((((unsigned long)(n))>>24)&0x1)
 252 #define DDR0_14_REDUC_MASK                0x00010000
 253 #define DDR0_14_REDUC_64BITS              0x00000000
 254 #define DDR0_14_REDUC_32BITS              0x00010000
 255 #define DDR0_14_REDUC_ENCODE(n)             ((((unsigned long)(n))&0x1)<<16)
 256 #define DDR0_14_REDUC_DECODE(n)             ((((unsigned long)(n))>>16)&0x1)
 257 #define DDR0_14_REG_DIMM_ENABLE_MASK      0x00000100
 258 #define DDR0_14_REG_DIMM_ENABLE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<8)
 259 #define DDR0_14_REG_DIMM_ENABLE_DECODE(n)   ((((unsigned long)(n))>>8)&0x1)
 260
 261 #define DDR0_15                         0x0F
 262
 263 #define DDR0_16                         0x10
 264
 265 #define DDR0_17                         0x11
 266 #define DDR0_17_DLL_DQS_DELAY_0_MASK      0x7F000000
 267 #define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
 268 #define DDR0_17_DLL_DQS_DELAY_0_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
 269 #define DDR0_17_DLLLOCKREG_MASK           0x00010000 /* Read only */
 270 #define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
 271 #define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
 272 #define DDR0_17_DLLLOCKREG_ENCODE(n)        ((((unsigned long)(n))&0x1)<<16)
 273 #define DDR0_17_DLLLOCKREG_DECODE(n)        ((((unsigned long)(n))>>16)&0x1)
 274 #define DDR0_17_DLL_LOCK_MASK             0x00007F00 /* Read only */
 275 #define DDR0_17_DLL_LOCK_ENCODE(n)          ((((unsigned long)(n))&0x7F)<<8)
 276 #define DDR0_17_DLL_LOCK_DECODE(n)          ((((unsigned long)(n))>>8)&0x7F)
 277
 278 #define DDR0_18                         0x12
 279 #define DDR0_18_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
 280 #define DDR0_18_DLL_DQS_DELAY_4_MASK      0x7F000000
 281 #define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
 282 #define DDR0_18_DLL_DQS_DELAY_4_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
 283 #define DDR0_18_DLL_DQS_DELAY_3_MASK      0x007F0000
 284 #define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
 285 #define DDR0_18_DLL_DQS_DELAY_3_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
 286 #define DDR0_18_DLL_DQS_DELAY_2_MASK      0x00007F00
 287 #define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
 288 #define DDR0_18_DLL_DQS_DELAY_2_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
 289 #define DDR0_18_DLL_DQS_DELAY_1_MASK      0x0000007F
 290 #define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
 291 #define DDR0_18_DLL_DQS_DELAY_1_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
 292
 293 #define DDR0_19                         0x13
 294 #define DDR0_19_DLL_DQS_DELAY_X_MASK      0x7F7F7F7F
 295 #define DDR0_19_DLL_DQS_DELAY_8_MASK      0x7F000000
 296 #define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
 297 #define DDR0_19_DLL_DQS_DELAY_8_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
 298 #define DDR0_19_DLL_DQS_DELAY_7_MASK      0x007F0000
 299 #define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
 300 #define DDR0_19_DLL_DQS_DELAY_7_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
 301 #define DDR0_19_DLL_DQS_DELAY_6_MASK      0x00007F00
 302 #define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
 303 #define DDR0_19_DLL_DQS_DELAY_6_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
 304 #define DDR0_19_DLL_DQS_DELAY_5_MASK      0x0000007F
 305 #define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
 306 #define DDR0_19_DLL_DQS_DELAY_5_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
 307
 308 #define DDR0_20                         0x14
 309 #define DDR0_20_DLL_DQS_BYPASS_3_MASK      0x7F000000
 310 #define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
 311 #define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
 312 #define DDR0_20_DLL_DQS_BYPASS_2_MASK      0x007F0000
 313 #define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
 314 #define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
 315 #define DDR0_20_DLL_DQS_BYPASS_1_MASK      0x00007F00
 316 #define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
 317 #define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
 318 #define DDR0_20_DLL_DQS_BYPASS_0_MASK      0x0000007F
 319 #define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
 320 #define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
 321
 322 #define DDR0_21                         0x15
 323 #define DDR0_21_DLL_DQS_BYPASS_7_MASK      0x7F000000
 324 #define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<24)
 325 #define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n)   ((((unsigned long)(n))>>24)&0x7F)
 326 #define DDR0_21_DLL_DQS_BYPASS_6_MASK      0x007F0000
 327 #define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<16)
 328 #define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n)   ((((unsigned long)(n))>>16)&0x7F)
 329 #define DDR0_21_DLL_DQS_BYPASS_5_MASK      0x00007F00
 330 #define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<8)
 331 #define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n)   ((((unsigned long)(n))>>8)&0x7F)
 332 #define DDR0_21_DLL_DQS_BYPASS_4_MASK      0x0000007F
 333 #define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
 334 #define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)
 335
 336 #define DDR0_22                         0x16
 337 /* ECC */
 338 #define DDR0_22_CTRL_RAW_MASK             0x03000000
 339 #define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000 /* ECC not being used */
 340 #define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000 /* ECC checking is on, but no attempts to correct*/
 341 #define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000 /* No ECC RAM storage available */
 342 #define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000 /* ECC checking and correcting on */
 343 #define DDR0_22_CTRL_RAW_ENCODE(n)          ((((unsigned long)(n))&0x3)<<24)
 344 #define DDR0_22_CTRL_RAW_DECODE(n)          ((((unsigned long)(n))>>24)&0x3)
 345
 346 #define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
 347 #define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
 348 #define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
 349 #define DDR0_22_DQS_OUT_SHIFT_MASK        0x00007F00
 350 #define DDR0_22_DQS_OUT_SHIFT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
 351 #define DDR0_22_DQS_OUT_SHIFT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
 352 #define DDR0_22_DLL_DQS_BYPASS_8_MASK     0x0000007F
 353 #define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n)  ((((unsigned long)(n))&0x7F)<<0)
 354 #define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n)  ((((unsigned long)(n))>>0)&0x7F)
 355
 356
 357 #define DDR0_23                         0x17
 358 #define DDR0_23_ODT_RD_MAP_CS0_MASK       0x03000000
 359 #define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n)   ((((unsigned long)(n))&0x3)<<24)
 360 #define DDR0_23_ODT_RD_MAP_CS0_DECODE(n)   ((((unsigned long)(n))>>24)&0x3)
 361 #define DDR0_23_ECC_C_SYND_MASK           0x00FF0000 /* Read only */
 362 #define DDR0_23_ECC_C_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
 363 #define DDR0_23_ECC_C_SYND_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
 364 #define DDR0_23_ECC_U_SYND_MASK           0x0000FF00 /* Read only */
 365 #define DDR0_23_ECC_U_SYND_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<8)
 366 #define DDR0_23_ECC_U_SYND_DECODE(n)        ((((unsigned long)(n))>>8)&0xFF)
 367 #define DDR0_23_FWC_MASK                  0x00000001 /* Write only */
 368 #define DDR0_23_FWC_ENCODE(n)               ((((unsigned long)(n))&0x1)<<0)
 369 #define DDR0_23_FWC_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
 370
 371 #define DDR0_24                         0x18
 372 #define DDR0_24_RTT_PAD_TERMINATION_MASK  0x03000000
 373 #define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
 374 #define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
 375 #define DDR0_24_ODT_WR_MAP_CS1_MASK       0x00030000
 376 #define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<16)
 377 #define DDR0_24_ODT_WR_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>16)&0x3)
 378 #define DDR0_24_ODT_RD_MAP_CS1_MASK       0x00000300
 379 #define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n)    ((((unsigned long)(n))&0x3)<<8)
 380 #define DDR0_24_ODT_RD_MAP_CS1_DECODE(n)    ((((unsigned long)(n))>>8)&0x3)
 381 #define DDR0_24_ODT_WR_MAP_CS0_MASK       0x00000003
 382 #define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n)    ((((unsigned long)(n))&0x3)<<0)
 383 #define DDR0_24_ODT_WR_MAP_CS0_DECODE(n)    ((((unsigned long)(n))>>0)&0x3)
 384
 385 #define DDR0_25                         0x19
 386 #define DDR0_25_VERSION_MASK              0xFFFF0000 /* Read only */
 387 #define DDR0_25_VERSION_ENCODE(n)           ((((unsigned long)(n))&0xFFFF)<<16)
 388 #define DDR0_25_VERSION_DECODE(n)           ((((unsigned long)(n))>>16)&0xFFFF)
 389 #define DDR0_25_OUT_OF_RANGE_LENGTH_MASK  0x000003FF /* Read only */
 390 #define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
 391 #define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
 392
 393 #define DDR0_26                         0x1A
 394 #define DDR0_26_TRAS_MAX_MASK             0xFFFF0000
 395 #define DDR0_26_TRAS_MAX_ENCODE(n)          ((((unsigned long)(n))&0xFFFF)<<16)
 396 #define DDR0_26_TRAS_MAX_DECODE(n)          ((((unsigned long)(n))>>16)&0xFFFF)
 397 #define DDR0_26_TREF_MASK                 0x00003FFF
 398 #define DDR0_26_TREF_ENCODE(n)              ((((unsigned long)(n))&0x3FFF)<<0)
 399 #define DDR0_26_TREF_DECODE(n)              ((((unsigned long)(n))>>0)&0x3FFF)
 400
 401 #define DDR0_27                         0x1B
 402 #define DDR0_27_EMRS_DATA_MASK            0x3FFF0000
 403 #define DDR0_27_EMRS_DATA_ENCODE(n)         ((((unsigned long)(n))&0x3FFF)<<16)
 404 #define DDR0_27_EMRS_DATA_DECODE(n)         ((((unsigned long)(n))>>16)&0x3FFF)
 405 #define DDR0_27_TINIT_MASK                0x0000FFFF
 406 #define DDR0_27_TINIT_ENCODE(n)             ((((unsigned long)(n))&0xFFFF)<<0)
 407 #define DDR0_27_TINIT_DECODE(n)             ((((unsigned long)(n))>>0)&0xFFFF)
 408
 409 #define DDR0_28                         0x1C
 410 #define DDR0_28_EMRS3_DATA_MASK           0x3FFF0000
 411 #define DDR0_28_EMRS3_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<16)
 412 #define DDR0_28_EMRS3_DATA_DECODE(n)        ((((unsigned long)(n))>>16)&0x3FFF)
 413 #define DDR0_28_EMRS2_DATA_MASK           0x00003FFF
 414 #define DDR0_28_EMRS2_DATA_ENCODE(n)        ((((unsigned long)(n))&0x3FFF)<<0)
 415 #define DDR0_28_EMRS2_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0x3FFF)
 416
 417 #define DDR0_29                         0x1D
 418
 419 #define DDR0_30                         0x1E
 420
 421 #define DDR0_31                         0x1F
 422 #define DDR0_31_XOR_CHECK_BITS_MASK       0x0000FFFF
 423 #define DDR0_31_XOR_CHECK_BITS_ENCODE(n)    ((((unsigned long)(n))&0xFFFF)<<0)
 424 #define DDR0_31_XOR_CHECK_BITS_DECODE(n)    ((((unsigned long)(n))>>0)&0xFFFF)
 425
 426 #define DDR0_32                         0x20
 427 #define DDR0_32_OUT_OF_RANGE_ADDR_MASK    0xFFFFFFFF /* Read only */
 428 #define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
 429 #define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
 430
 431 #define DDR0_33                         0x21
 432 #define DDR0_33_OUT_OF_RANGE_ADDR_MASK    0x00000001 /* Read only */
 433 #define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
 434 #define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n)               ((((unsigned long)(n))>>0)&0x1)
 435
 436 #define DDR0_34                         0x22
 437 #define DDR0_34_ECC_U_ADDR_MASK           0xFFFFFFFF /* Read only */
 438 #define DDR0_34_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
 439 #define DDR0_34_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
 440
 441 #define DDR0_35                         0x23
 442 #define DDR0_35_ECC_U_ADDR_MASK           0x00000001 /* Read only */
 443 #define DDR0_35_ECC_U_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
 444 #define DDR0_35_ECC_U_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
 445
 446 #define DDR0_36                         0x24
 447 #define DDR0_36_ECC_U_DATA_MASK           0xFFFFFFFF /* Read only */
 448 #define DDR0_36_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
 449 #define DDR0_36_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
 450
 451 #define DDR0_37                         0x25
 452 #define DDR0_37_ECC_U_DATA_MASK           0xFFFFFFFF /* Read only */
 453 #define DDR0_37_ECC_U_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
 454 #define DDR0_37_ECC_U_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
 455
 456 #define DDR0_38                         0x26
 457 #define DDR0_38_ECC_C_ADDR_MASK           0xFFFFFFFF /* Read only */
 458 #define DDR0_38_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
 459 #define DDR0_38_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
 460
 461 #define DDR0_39                         0x27
 462 #define DDR0_39_ECC_C_ADDR_MASK           0x00000001 /* Read only */
 463 #define DDR0_39_ECC_C_ADDR_ENCODE(n)        ((((unsigned long)(n))&0x1)<<0)
 464 #define DDR0_39_ECC_C_ADDR_DECODE(n)        ((((unsigned long)(n))>>0)&0x1)
 465
 466 #define DDR0_40                         0x28
 467 #define DDR0_40_ECC_C_DATA_MASK           0xFFFFFFFF /* Read only */
 468 #define DDR0_40_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
 469 #define DDR0_40_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
 470
 471 #define DDR0_41                         0x29
 472 #define DDR0_41_ECC_C_DATA_MASK           0xFFFFFFFF /* Read only */
 473 #define DDR0_41_ECC_C_DATA_ENCODE(n)        ((((unsigned long)(n))&0xFFFFFFFF)<<0)
 474 #define DDR0_41_ECC_C_DATA_DECODE(n)        ((((unsigned long)(n))>>0)&0xFFFFFFFF)
 475
 476 #define DDR0_42                         0x2A
 477 #define DDR0_42_ADDR_PINS_MASK            0x07000000
 478 #define DDR0_42_ADDR_PINS_ENCODE(n)         ((((unsigned long)(n))&0x7)<<24)
 479 #define DDR0_42_ADDR_PINS_DECODE(n)         ((((unsigned long)(n))>>24)&0x7)
 480 #define DDR0_42_CASLAT_LIN_GATE_MASK      0x0000000F
 481 #define DDR0_42_CASLAT_LIN_GATE_ENCODE(n)   ((((unsigned long)(n))&0xF)<<0)
 482 #define DDR0_42_CASLAT_LIN_GATE_DECODE(n)   ((((unsigned long)(n))>>0)&0xF)
 483
 484 #define DDR0_43                         0x2B
 485 #define DDR0_43_TWR_MASK                  0x07000000
 486 #define DDR0_43_TWR_ENCODE(n)               ((((unsigned long)(n))&0x7)<<24)
 487 #define DDR0_43_TWR_DECODE(n)               ((((unsigned long)(n))>>24)&0x7)
 488 #define DDR0_43_APREBIT_MASK              0x000F0000
 489 #define DDR0_43_APREBIT_ENCODE(n)           ((((unsigned long)(n))&0xF)<<16)
 490 #define DDR0_43_APREBIT_DECODE(n)           ((((unsigned long)(n))>>16)&0xF)
 491 #define DDR0_43_COLUMN_SIZE_MASK          0x00000700
 492 #define DDR0_43_COLUMN_SIZE_ENCODE(n)       ((((unsigned long)(n))&0x7)<<8)
 493 #define DDR0_43_COLUMN_SIZE_DECODE(n)       ((((unsigned long)(n))>>8)&0x7)
 494 #define DDR0_43_EIGHT_BANK_MODE_MASK      0x00000001
 495 #define DDR0_43_EIGHT_BANK_MODE_8_BANKS     0x00000001
 496 #define DDR0_43_EIGHT_BANK_MODE_4_BANKS     0x00000000
 497 #define DDR0_43_EIGHT_BANK_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<0)
 498 #define DDR0_43_EIGHT_BANK_MODE_DECODE(n)   ((((unsigned long)(n))>>0)&0x1)
 499
 500 #define DDR0_44                         0x2C
 501 #define DDR0_44_TRCD_MASK                 0x000000FF
 502 #define DDR0_44_TRCD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<0)
 503 #define DDR0_44_TRCD_DECODE(n)              ((((unsigned long)(n))>>0)&0xFF)
 504
 505 #endif /* _SPD_SDRAM_DENALI_H_ */