board/m5271evb/m5271evb.c

   1 /*
   2  * (C) Copyright 2000-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/immap.h>
  26
  27 int checkboard (void) {
  28         puts ("Board: Freescale M5271EVB\n");
  29         return 0;
  30 };
  31
  32 long int initdram (int board_type) {
  33
  34         int i;
  35
  36         /* Enable Address lines 23-21 and lower 16bits of data path */
  37         mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 |
  38                         MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 |
  39                         MCF_GPIO_AD_DATAL);
  40
  41         /* Set CS2 pin to be SD_CS0 */
  42         mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
  43                         | MCF_GPIO_PAR_CS_PAR_CS2);
  44
  45         /* Configure SDRAM Control Pin Assignemnt Register */
  46         mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 |
  47                         MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
  48                         MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
  49                         MCF_GPIO_SDRAM_SDCS_11);
  50
  51         /*
  52          * Check to see if the SDRAM has already been initialized
  53          * by a run control tool
  54          */
  55         if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
  56                 /* Initialize DRAM Control Register: DCR */
  57                 mbar_writeShort(MCF_SDRAMC_DCR,
  58                                 MCF_SDRAMC_DCR_RTIM(0x01)
  59                                 | MCF_SDRAMC_DCR_RC(0x30));
  60
  61                 /*
  62                  * Initialize DACR0
  63                  *
  64                  * CASL: 01
  65                  * CBM: cmd at A20, bank select bits 21 and up
  66                  * PS: 32bit port size
  67                  */
  68                 mbar_writeLong(MCF_SDRAMC_DACR0,
  69                                 MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
  70                                 | MCF_SDRAMC_DACRn_CASL(1)
  71                                 | MCF_SDRAMC_DACRn_CBM(3)
  72                                 | MCF_SDRAMC_DACRn_PS(0));
  73
  74                 /* Initialize DMR0 */
  75                 mbar_writeLong(MCF_SDRAMC_DMR0,
  76                                 MCF_SDRAMC_DMRn_BAM_16M
  77                                 | MCF_SDRAMC_DMRn_V);
  78
  79                 /* Set IP bit in DACR */
  80                 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
  81                                 | MCF_SDRAMC_DACRn_IP);
  82
  83                 /* Wait at least 20ns to allow banks to precharge */
  84                 for (i = 0; i < 5; i++)
  85                         asm(" nop");
  86
  87                 /* Write to this block to initiate precharge */
  88                 *(u32 *)(CFG_SDRAM_BASE) = 0xa5a5a5a5;
  89
  90                 /* Set RE bit in DACR */
  91                 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
  92                                 | MCF_SDRAMC_DACRn_RE);
  93
  94                 /* Wait for at least 8 auto refresh cycles to occur */
  95                 for (i = 0; i < 2000; i++)
  96                         asm(" nop");
  97
  98                 /* Finish the configuration by issuing the MRS */
  99                 mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
 100                                 | MCF_SDRAMC_DACRn_MRS);
 101
 102                 /*
 103                  * Write to the SDRAM Mode Register A0-A11 = 0x400
 104                  *
 105                  * Write Burst Mode = Programmed Burst Length
 106                  * Op Mode = Standard Op
 107                  * CAS Latency = 2
 108                  * Burst Type = Sequential
 109                  * Burst Length = 1
 110                  */
 111                 *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
 112         }
 113
 114         return CFG_SDRAM_SIZE * 1024 * 1024;
 115 };
 116
 117 int testdram (void) {
 118
 119         /* TODO: XXX XXX XXX */
 120         printf ("DRAM test not implemented!\n");
 121
 122         return (0);
 123 }