board/m5282evb/m5282evb.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/immap.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 int checkboard (void)
  30 {
  31         puts ("Board: Freescale M5282EVB Evaluation Board\n");
  32         return 0;
  33 }
  34
  35 long int initdram (int board_type)
  36 {
  37         u32 dramsize, i, dramclk;
  38
  39         dramsize = CFG_SDRAM_SIZE * 0x100000;
  40         for (i = 0x13; i < 0x20; i++) {
  41                 if (dramsize == (1 << i))
  42                         break;
  43         }
  44         i--;
  45
  46         if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
  47         {
  48                 dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
  49
  50                 /* Initialize DRAM Control Register: DCR */
  51                 MCFSDRAMC_DCR = (0
  52                         | MCFSDRAMC_DCR_RTIM_6
  53                         | MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
  54
  55                 /* Initialize DACR0 */
  56                 MCFSDRAMC_DACR0 = (0
  57                         | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE)
  58                         | MCFSDRAMC_DACR_CASL(1)
  59                         | MCFSDRAMC_DACR_CBM(3)
  60                         | MCFSDRAMC_DACR_PS_32);
  61
  62                 /* Initialize DMR0 */
  63                 MCFSDRAMC_DMR0 = (0
  64                         | ((dramsize - 1) & 0xFFFC0000)
  65                         | MCFSDRAMC_DMR_V);
  66
  67                 /* Set IP (bit 3) in DACR */
  68                 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
  69
  70                 /* Wait 30ns to allow banks to precharge */
  71                 for (i = 0; i < 5; i++) {
  72                         asm ("nop");
  73                 }
  74
  75                 /* Write to this block to initiate precharge */
  76                 *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696;
  77
  78                 /* Set RE (bit 15) in DACR */
  79                 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
  80
  81                 /* Wait for at least 8 auto refresh cycles to occur */
  82                 for (i = 0; i < 2000; i++) {
  83                         asm(" nop");
  84                 }
  85
  86                 /* Finish the configuration by issuing the IMRS. */
  87                 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
  88
  89                 /* Write to the SDRAM Mode Register */
  90                 *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
  91         }
  92         return dramsize;
  93 }