board/matrix_vision/mvblm7/fpga.c

   1 /*
   2  * (C) Copyright 2002
   3  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
   4  * Keith Outwater, keith_outwater@mvis.com.
   5  *
   6  * (C) Copyright 2008
   7  * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  *
  27  */
  28
  29 #include <common.h>
  30 #include <ACEX1K.h>
  31 #include <command.h>
  32 #include "fpga.h"
  33 #include "mvblm7.h"
  34
  35 #ifdef FPGA_DEBUG
  36 #define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
  37 #else
  38 #define fpga_debug(fmt, args...)
  39 #endif
  40
  41 Altera_CYC2_Passive_Serial_fns altera_fns = {
  42         fpga_null_fn,
  43         fpga_config_fn,
  44         fpga_status_fn,
  45         fpga_done_fn,
  46         fpga_wr_fn,
  47         fpga_null_fn,
  48         fpga_null_fn,
  49 };
  50
  51 Altera_desc cyclone2 = {
  52         Altera_CYC2,
  53         passive_serial,
  54         Altera_EP2C20_SIZE,
  55         (void *) &altera_fns,
  56         NULL,
  57         0
  58 };
  59
  60 DECLARE_GLOBAL_DATA_PTR;
  61
  62 int mvblm7_init_fpga(void)
  63 {
  64         fpga_debug("Initialize FPGA interface\n");
  65         fpga_init();
  66         fpga_add(fpga_altera, &cyclone2);
  67         fpga_config_fn(0, 1, 0);
  68         udelay(60);
  69
  70         return 1;
  71 }
  72
  73 int fpga_null_fn(int cookie)
  74 {
  75         return 0;
  76 }
  77
  78 int fpga_config_fn(int assert, int flush, int cookie)
  79 {
  80         volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  81         volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
  82         u32 dvo = gpio->dat;
  83
  84         fpga_debug("SET config : %s\n", assert ? "low" : "high");
  85         if (assert)
  86                 dvo |= FPGA_CONFIG;
  87         else
  88                 dvo &= ~FPGA_CONFIG;
  89
  90         if (flush)
  91                 gpio->dat = dvo;
  92
  93         return assert;
  94 }
  95
  96 int fpga_done_fn(int cookie)
  97 {
  98         volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  99         volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 100         int result = 0;
 101
 102         udelay(10);
 103         fpga_debug("CONF_DONE check ... ");
 104         if (gpio->dat & FPGA_CONF_DONE)  {
 105                 fpga_debug("high\n");
 106                 result = 1;
 107         } else
 108                 fpga_debug("low\n");
 109
 110         return result;
 111 }
 112
 113 int fpga_status_fn(int cookie)
 114 {
 115         volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 116         volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 117         int result = 0;
 118
 119         fpga_debug("STATUS check ... ");
 120         if (gpio->dat & FPGA_STATUS)  {
 121                 fpga_debug("high\n");
 122                 result = 1;
 123         } else
 124                 fpga_debug("low\n");
 125
 126         return result;
 127 }
 128
 129 int fpga_clk_fn(int assert_clk, int flush, int cookie)
 130 {
 131         volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 132         volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 133         u32 dvo = gpio->dat;
 134
 135         fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
 136         if (assert_clk)
 137                 dvo |= FPGA_CCLK;
 138         else
 139                 dvo &= ~FPGA_CCLK;
 140
 141         if (flush)
 142                 gpio->dat = dvo;
 143
 144         return assert_clk;
 145 }
 146
 147 static inline int _write_fpga(u8 val, int dump)
 148 {
 149         volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 150         volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 151         int i;
 152         u32 dvo = gpio->dat;
 153
 154         if (dump)
 155                 fpga_debug("  %02x -> ", val);
 156         for (i = 0; i < 8; i++) {
 157                 dvo &= ~FPGA_CCLK;
 158                 gpio->dat = dvo;
 159                 dvo &= ~FPGA_DIN;
 160                 if (dump)
 161                         fpga_debug("%d ", val&1);
 162                 if (val & 1)
 163                         dvo |= FPGA_DIN;
 164                 gpio->dat = dvo;
 165                 dvo |= FPGA_CCLK;
 166                 gpio->dat = dvo;
 167                 val >>= 1;
 168         }
 169         if (dump)
 170                 fpga_debug("\n");
 171
 172         return 0;
 173 }
 174
 175 int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
 176 {
 177         unsigned char *data = (unsigned char *) buf;
 178         int i;
 179
 180         fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
 181         for (i = 0; i < len; i++)
 182                 _write_fpga(data[i], 0);
 183         fpga_debug("\n");
 184
 185         return FPGA_SUCCESS;
 186 }